Datasheet

18
ATtiny11/12
1006D–AVR–07/03
Power-on Reset for the
ATtiny11
A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As
shown in Figure 16, an internal timer is clocked from the watchdog timer. This timer pre-
vents the MCU from starting a certain period after V
CC
has reached the Power-on
Threshold Voltage – V
POT
. See Figure 18. The total reset period is the Delay Time-out
period – t
TOUT
. The FSTRT fuse bit in the Flash can be programmed to give a shorter
start-up time.The start-up times for the different clock options are shown in the following
table. The Watchdog Oscillator is used for timing the start-up time, and this oscillator is
voltage dependent as shown in the section “ATtiny11 Typical Characteristics” on page
60.
If the built-in start-up delay is sufficient, RESET
can be connected to V
CC
directly or via
an external pull-up resistor. By holding the RESET
pin low for a period after V
CC
has
been applied, the Power-on Reset period can be extended. Refer to Figure 19 for a tim-
ing example on this.
Table 7. Start-up Times for the ATtiny11 (V
CC
= 2.7V)
Selected Clock Option
Start-up Time t
TOUT
FSTRT Unprogrammed FSTRT Programmed
External Crystal 67 ms 4.2 ms
External Ceramic Resonator 67 ms 4.2 ms
External Low-frequency Crystal 4.2 s 4.2 s
External RC Oscillator 4.2 ms 67 µs
Internal RC Oscillator 4.2 ms 67 µs
External Clock 4.2 ms
5 clocks from reset,
2 clocks from power-down