Features • Utilizes the AVR® RISC Architecture • High-performance and Low-power 8-bit RISC Architecture • • • • • • • • – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 8 MIPS Throughput at 8 MHz Nonvolatile Program and Data Memory – 1K Byte of Flash Program Memory In-System Programmable (ATtiny12) Endurance: 1,000 Write/Erase Cycles (ATtiny11/12) – 64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12 Endurance: 100,000 Wr
Description The ATtiny11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny11/12 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working registers.
ATtiny11/12 Figure 1. The ATtiny11 Block Diagram VCC 8-BIT DATA BUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER WATCHDOG TIMER PROGRAM FLASH HARDWARE STACK MCU CONTROL REGISTER INSTRUCTION REGISTER GENERALPURPOSE REGISTERS INSTRUCTION DECODER CONTROL LINES TIMING AND CONTROL MCU STATUS REGISTER Z TIMER/ COUNTER ALU INTERRUPT UNIT STATUS REGISTER ANALOG COMPARATOR + - PROGRAMMING LOGIC OSCILLATORS DATA REGISTER PORTB DATA DIR. REG.
ATtiny12 Block Diagram Figure 2.
ATtiny11/12 The ATtiny12 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Pin Descriptions VCC Supply voltage pin. GND Ground pin. Port B (PB5..PB0) Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output.
Table 3. Device Clocking Options Select (Continued) Device Clocking Option ATtiny11 CKSEL2..0 ATtiny12 CKSEL3..0 Internal RC Oscillator 100 0100 - 0010 External Clock 000 0001 - 0000 Reserved Other Options Note: “1” means unprogrammed, “0” means programmed. - The various choices for each clocking option give different start-up times as shown in Table 7 on page 18 and Table 9 on page 20.
ATtiny11/12 External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 5 can be used. For details on how to choose R and C, see Table 29 on page 59. The external RC oscillator is sensitive to noise from neighboring pins, and to avoid problems, PB5 (RESET) should be used as an output or reset pin, and PB4 should be used as an output pin. Figure 5.
Architectural Overview The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single-clock-cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file – in one clock cycle. Two of the 32 registers can be used as a 16-bit pointer for indirect memory access.
ATtiny11/12 Figure 6.
OR and all other operations between two registers or on a single register apply to the entire register file. Registers 30 and 31 form a 16-bit pointer (the Z-pointer) which is used for indirect Flash memory and register file access. When the register file is accessed, the contents of R31 are discarded by the CPU. ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers.
ATtiny11/12 Register Indirect Figure 9. Indirect Register Addressing REGISTER FILE 0 Z-register 30 31 The register accessed is the one pointed to by the Z-register (R31, R30). Register Direct, Two Registers Rd and Rr Figure 10. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O Direct Figure 11. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word.
Relative Program Addressing, RJMP and RCALL Figure 12. Relative Program Memory Addressing +1 Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047. Constant Addressing Using the LPM Instruction Figure 13. Code Memory Constant Addressing PROGRAM MEMORY $000 15 1 0 Z-REGISTER $1FF Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), the LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
ATtiny11/12 EEPROM Data Memory The ATtiny12 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 38, specifying the EEPROM Address Register, the EEPROM Data Register, and the EEPROM Control Register. For SPI data downloading, see “Memory Programming” on page 46 for a detailed description.
I/O Memory The I/O space definition of the ATtiny11/12 is shown in the following table: Table 4.
ATtiny11/12 global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. • Bit 6 - T: Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit.
Table 5. Reset and Interrupt Vectors Vector No.
ATtiny11/12 Reset Sources The ATtiny11/12 provides three or four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (VPOT). • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. • Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled. • Brown-out Reset. The MCU is reset when the supply voltage VCC falls below a certain voltage (ATtiny12 only).
Power-on Reset for the ATtiny11 A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 16, an internal timer is clocked from the watchdog timer. This timer prevents the MCU from starting a certain period after V CC has reached the Power-on Threshold Voltage – VPOT. See Figure 18. The total reset period is the Delay Time-out period – tTOUT. The FSTRT fuse bit in the Flash can be programmed to give a shorter start-up time.
ATtiny11/12 Figure 17. Reset Logic for the ATtiny12 DATA BUS Power-on Reset Circuit BODEN BODLEVEL PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Brown-out Reset Circuit CKSEL[3:0] On-chip RC Oscillator Delay Counters Full CK Table 8. Reset Characteristics for the ATtiny12 Symbol Parameter Condition Min Typ Max Units Power-on Reset Threshold Voltage (rising) BOD disabled 1.0 1.4 1.8 V BOD enabled 0.6 1.2 1.8 V Power-on Reset Threshold Voltage (falling) BOD disabled 0.4 0.
Table 9. ATtiny12 Clock Options and Start-up Times Clock Source Start-up Time, VCC = 1.8V, BODLEVEL Unprogrammed Start-up Time, VCC = 2.7V, BODLEVEL Programmed 1111 Ext. Crystal/Ceramic Resonator(1) 1K CK 1K CK 1110 Ext. Crystal/Ceramic Resonator(1) 3.6 ms + 1K CK 4.2 ms + 1K CK 1101 (1) Ext. Crystal/Ceramic Resonator 57 ms 1K CK 67 ms + 1K CK 1100 Ext. Crystal/Ceramic Resonator 16K CK 16K CK 1011 Ext. Crystal/Ceramic Resonator 3.6 ms + 16K CK 4.2 ms + 16K CK 1010 Ext.
ATtiny11/12 Power-on Reset for the ATtiny12 A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is nominally 1.4V. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the start-up reset, as well as detect a failure in supply voltage. The Power-on Reset (POR) circuit ensures that the device is reset from power-on.
Figure 20. External Reset during Operation VCC RESET VRST t TOUT TIME-OUT INTERNAL RESET Brown-out Detection (ATtiny12) ATtiny12 has an on-chip brown-out detection (BOD) circuit for monitoring the VCC level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and VCC decreases below the trigger level, the brown-out reset is immediately activated.
ATtiny11/12 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period (tTOUT). Refer to page 36 for details on operation of the Watchdog. Figure 22. Watchdog Reset during Operation VCC CK MCU Status Register – MCUSR of the ATtiny11 The MCU Status Register provides information on which reset source caused an MCU reset.
before the bits are cleared. If the bit is cleared before an external or watchdog reset occurs, the source of reset can be found by using the following truth table: Table 12. Reset Source Identification MCU Status Register – MCUSR for the ATtiny12 EXTRF PORF Reset Source 0 0 Watchdog Reset 1 0 External Reset 0 1 Power-on Reset 1 1 Power-on Reset The MCU Status Register provides information on which reset source caused an MCU reset.
ATtiny11/12 1. When BOD is enabled (by programming the BODEN fuse) 2. When the bandgap reference is connected to the Analog Comparator (by setting the AINBG bit in ACSR) Thus, when BOD is not enabled, after setting the AINBG bit, the user must always allow the reference to start up before the output from the Analog Comparator is used. The bandgap reference uses approximately 10 µA, and to reduce power consumption in Power-down mode, the user can turn off the reference when entering this mode.
• Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny11/12 and always reads as zero. • Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) define whether the external interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin.
ATtiny11/12 $39 - - - - - - TOIE0 - Read/Write R R R R R R R/W R Initial Value 0 0 0 0 0 0 0 0 TIMSK • Bit 7..2 - Res: Reserved Bits These bits are reserved bits in the ATtiny11/12 and always read as zero. • Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled.
another interrupt, for example, the external interrupt. This implies that one external event might cause several interrupts. The values on the pins are sampled before detecting edges. If pin change interrupt is enabled, pulses that last longer than one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
ATtiny11/12 MCU Control Register – MCUCR The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 $35 - (PUD) SE SM - - ISC01 ISC00 Read/Write R R(/W) R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR The Pull-up Disable (PUD) bit is only available in ATtiny12. • Bit 7 - Res: Reserved Bit This bit is a reserved bit in the ATtiny11/12 and always reads as zero.
instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low.
ATtiny11/12 Sleep Modes for the ATtiny11 To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. The SM bit in the MCUCR register selects which sleep mode (Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP.
Note that if a level triggered or pin change interrupt is used for wake-up from Powerdown Mode, the changed level must be held for a time to wake up the MCU. This makes the MCU less sensitive to noise. The wake-up period is equal to the clock-counting part of the reset period (See Table 9). The MCU will wake up from the power-down if the input has the required level for two watchdog oscillator cycles.
ATtiny11/12 Timer/Counter0 The ATtiny11/12 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. The Timer/Counter0 has prescaling selection from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock timebase or as a counter with an external pin connection that triggers the counting. Timer/Counter Prescaler Figure 23 shows the Timer/Counter prescaler. Figure 23.
Figure 24. Timer/Counter0 Block Diagram T0 Timer/Counter0 Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 $33 - - - - - CS02 CS01 CS00 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bits 7..3 - Res: Reserved Bits These bits are reserved bits in the ATtiny11/12 and always read as zero. • Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, Bit 2,1 and 0 The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0. Table 15.
ATtiny11/12 The Stop condition provides a Timer Enable/Disable function. The CK down-divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting.
Watchdog Timer The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 16. See characterization data for typical values at other VCC levels. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period.
ATtiny11/12 1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog. • Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0 The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
ATtiny12 EEPROM Read/Write Access The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 3.1 - 6.8 ms, depending on the frequency of the calibrated RC oscillator. See Table 17 for details. A self-timing function lets the user software detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to accept new data. The minimum voltage for writing to the EEPROM is 2.2V.
ATtiny11/12 • Bit 2 - EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.
Prevent EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
ATtiny11/12 Analog Comparator The Analog Comparator compares the input values on the positive input PB0 (AIN0) and negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output (ACO) is set (one). The comparator’s output can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select interrupt triggering on comparator output rise, fall or toggle.
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. • Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 - Res: Reserved Bit This bit is a reserved bit in the ATtiny11/12 and will always read as zero.
ATtiny11/12 I/O Port B All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Port B is a 6-bit bi-directional I/O port.
Port B Data Register – PORTB Port B Data Direction Register – DDRB Bit 7 6 5 4 3 2 1 0 $18 - - - PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 $17 - - (DDB5) DDB4 DDB3 DDB2 DDB1 DDB0 Read/Write R R R(/W) R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: Port B Input Pins Address – PINB PORTB DDRB DDB5 is only available in ATtiny12.
ATtiny11/12 Alternate Functions of Port B All port B pins are connected to a pin change detector that can trigger the pin change interrupt. See “Pin Change Interrupt” on page 27 for details. In addition, Port B has the following alternate functions: • RESET - Port B, Bit 5 When the RSTDISBL fuse is unprogrammed, this pin serves as external reset. When the RSTDISBL fuse is programmed, this pin is a general input pin. In ATtiny12, it is also an open-drain output pin.
Memory Programming Program (and Data) Memory Lock Bits The ATtiny11/12 MCU provides two lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 21. The lock bits can only be erased with the Chip Erase command. Table 21. Lock Bit Protection Modes Memory Lock Bits Mode LB1 LB2 1 1 1 No memory lock features enabled. 2 0 1 Further programming of the Flash (and EEPROM for ATtiny12) is disabled.
ATtiny11/12 • CKSEL3..0 fuses: See Table 3, “Device Clocking Options Select,” on page 5 and Table 9, “ATtiny12 Clock Options and Start-up Times,” on page 20, for which combination of CKSEL3..0 to use. Default value is “0010”, internal RC oscillator with long start-up time. The status of the fuse bits is not affected by Chip Erase. Note: Signature Bytes 1. If the RSTDISBL Fuse is programmed, then the programming hardware should apply +12V to PB5 while the ATtiny12 is in Power-on Reset.
provides a convenient way to download program and data into the ATtiny12 inside the user’s system. The program and data memory arrays in the ATtiny12 are programmed byte-by-byte in either programming mode. For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction in the Low-voltage Serial Programming mode. ATtiny11/12 During programming, the supply voltage must be in accordance with Table 22. Table 22.
ATtiny11/12 High-voltage Serial Programming Algorithm To program and verify the ATtiny11/12 in the High-voltage Serial Programming mode, the following sequence is recommended (See instruction formats in Table 23): 1. Power-up sequence: Apply 4.5 - 5.5V between VCC and GND. Set PB5 and PB0 to “0” and wait at least 100 ns. Toggle PB3 at least four times with minimum 100 ns pulse-width. Set PB3 to “0”. Wait at least 100 ns. Apply 12V to PB5 and wait at least 100 ns before changing PB0.
Figure 28. High-voltage Serial Programming Waveforms SERIAL DATA INPUT PB0 MSB LSB SERIAL INSTR. INPUT PB1 MSB LSB SERIAL DATA OUTPUT PB2 SERIAL CLOCK INPUT XTAL1/PB3 MSB 0 LSB 1 2 3 4 5 6 7 8 9 10 Table 23. High-voltage Serial Programming Instruction Set for ATtiny11/12 Instruction Format Instruction Instr.1 Instr.2 Instr.3 Instr.
ATtiny11/12 Table 23. High-voltage Serial Programming Instruction Set for ATtiny11/12 (Continued) Instruction Format Instruction Instr.1 Instr.
High-voltage Serial Programming Characteristics Figure 29. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) tIVSH SCI (PB3) tSHIX tSLSH tSHSL SDO (PB2) tSHOV Table 24. High-voltage Serial Programming Characteristics TA = 25°C ± 10%, VCC = 5.
ATtiny11/12 If the chip Erase command in Low-voltage Serial Programming is executed only once, one data byte may be written to the flash after erase. Using the following algorithm guarantees that the flash will be erased: • Execute a chip erase command • Write $FF to address $00 in the flash • Execute a second chip erase command For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first execute the Chip Erase instruction.
next instruction. See Table 28 on page 56 for tWD_FLASH and tWD_EEPROM values. In an erased device, no $FFs in the data file(s) needs to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at the serial output MISO (PB1) pin. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set XTAL1 to “0” (if external clocking is used). Set RESET to “1”.
ATtiny11/12 Table 25. Low-voltage Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable serial programming while RESET is low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip erase Flash and EEPROM memory arrays. 0010 H000 xxxx xxxa bbbb bbbb oooo oooo Read H (high or low) data o from program memory at word address a:b.
Low-voltage Serial Programming Characteristics Figure 32. Low-voltage Serial Programming Timing MOSI tOVSH SCK tSHOX tSLSH tSHSL MISO tSLIV Table 26. Low-voltage Serial Programming Characteristics TA = -40°C to 85°C, VCC = 2.2 - 5.5V (Unless otherwise noted) Symbol Parameter 1/tCLCL Oscillator Frequency (VCC = 2.2 - 2.7V) tCLCL Oscillator Period (VCC = 2.2 - 2.7V) 1/tCLCL Oscillator Frequency (VCC = 2.7 - 4.0V) tCLCL Oscillator Period (VCC = 2.7 - 4.
ATtiny11/12 Electrical Characteristics Absolute Maximum Ratings Operating Temperature .................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1.0V to VCC+0.5V Voltage on RESET with respect to Ground......-1.0V to +13.0V Stresses beyond those ratings listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DC Characteristics – Preliminary Data (Continued) TA = -40°C to 85°C, VCC = 2.7V to 5.5V for ATtiny11, VCC = 1.8V to 5.5V for ATtiny12 (Unless otherwise noted) Symbol ICC Parameter Power Supply Current Condition Max Units Active 1 MHz, VCC = 3V (ATtiny12V) 1.0 mA Active 2 MHz, VCC = 3V (ATtiny11L) 2.0 mA Active 4 MHz, VCC = 3V (ATtiny12L) 2.5 mA Active 6 MHz, VCC = 5V (ATtiny11) 10 mA Active 8 MHz, VCC = 5V (ATtiny12) 10 mA Idle 1 MHz, VCC = 3V (ATtiny12V) 0.
ATtiny11/12 External Clock Drive Waveforms Figure 33. External Clock VIH1 VIL1 External Clock Drive ATtiny11 VCC = 2.7V to 4.0V Symbol Parameter 1/tCLCL Oscillator Frequency VCC = 4.0V to 5.5V Min Max Min Max Units 0 2 0 6 MHz tCLCL Clock Period 500 167 ns tCHCX High Time 200 67 ns tCLCX Low Time 200 67 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.5 µs External Clock Drive ATtiny12 VCC = 1.8V to 2.7V VCC = 2.7V to 4.0V VCC = 4.0V to 5.
ATtiny11 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The power consumption in Power-down Mode is independent of clock selection.
ATtiny11/12 Figure 35. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 10 9 8 TA = 25˚C 7 TA = 85˚C ICC (mA) 6 5 4 3 2 1 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 36. Active Supply Current vs. VCC, Device Clocked by Internal Oscillator ACTIVE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 1.0MHz INTERNAL RC OSCILLATOR 6 5 TA = 25˚C 4 I cc(mA) TA = 85˚C 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
Figure 37. Active Supply Current vs. VCC, Device Clocked by External 32kHz Crystal ACTIVE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 32KHz CRYSTAL 5 4.5 4 TA = 25˚C 3.5 TA = 85˚C I cc(mA) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 38. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY TA = 25˚C 5 VCC = 6V 4.5 4 VCC = 5.5V 3.5 VCC = 5V ICC (mA) 3 VCC = 4.5V 2.5 VCC = 4V 2 VCC = 3.6V 1.5 VCC = 3.3V 1 VCC = 3.0V VCC = 2.7V 0.5 0 0 VCC = 2.4V VCC = 2.
ATtiny11/12 Figure 39. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc FREQUENCY = 4 MHz 3 TA = 25˚C 2 ICC (mA) TA = 85˚C 2 1 1 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 40. Idle Supply Current vs. VCC, Device Clocked by Internal Oscillator IDLE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 1.0MHz INTERNAL RC OSCILLATOR 0.35 0.3 TA = 25˚C 0.25 TA = 85˚C I cc(mA) 0.2 0.15 0.1 0.05 0 2.5 3 3.5 4 4.5 5 5.
Figure 41. Idle Supply Current vs. VCC, Device Clocked by External 32kHz Crystal IDLE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 32KHz CRYSTAL 25 20 TA = 25˚C TA = 85˚C I cc(µA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 42. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 9 TA = 85˚C 8 ICC (µA) 7 6 5 4 3 2 1 TA = 25˚C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny11/12 Figure 43. Power-down Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 90 80 70 I CC (µA) 60 TA = 85˚C TA = 25˚C 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC (V) Figure 44. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 1 0.9 0.8 TA = 25˚C I CC (mA) 0.7 TA = 85˚C 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Analog comparator offset voltage is measured as absolute offset. Figure 45. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE Vcc = 5V 18 16 TA = 25˚C Offset Voltage (mV) 14 12 TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 46. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. Vcc = 2.
ATtiny11/12 Figure 47. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 IACLK (nA) 40 30 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 VIN (V) Figure 48. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. Vcc 1600 1400 TA = 25˚C 1200 TA = 85˚C FRC (kHz) 1000 800 600 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 49. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 5V 120 TA = 25˚C 100 TA = 85˚C I OP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 Figure 50. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 30 TA = 25˚C 25 TA = 85˚C I OP (µA) 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATtiny11/12 Figure 51. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 5V 80 70 TA = 25˚C 60 I OL (mA) 50 40 TA = 85˚C 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 52. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 5V 18 TA = 25˚C 16 14 TA = 85˚C I OH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 53. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 30 TA = 25˚C 25 20 I OL (mA) TA = 85˚C 15 10 5 0 0 0.5 1 1.5 2 VOL (V) Figure 54. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE VCC = 2.7V 6 TA = 25˚C 5 4 I OH (mA) TA = 85˚C 3 2 1 0 0 0.5 1 1.5 2 2.
ATtiny11/12 Figure 55. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25˚C 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.0 VCC Figure 56. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25˚C 0.18 Input Hysteresis (V) 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.
ATtiny12 Typical Characteristics The following charts show typical behavior. These data are characterized, but not tested. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down Mode is independent of clock selection.
ATtiny11/12 Figure 58. Active Supply Current vs. VCC, Device Clocked by External 32kHz Crystal ACTIVE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 32KHz CRYSTAL 140 120 TA = 85˚C 100 I cc(µΑ) TA = 25˚C 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Figure 59. Idle Supply Current vs. VCC, Device Clocked by Internal Oscillator IDLE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 1.2MHz INTERNAL RC OSCILLATOR 0.8 0.7 TA = 25˚C 0.6 TA = 85˚C I cc(mΑ) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.
Figure 60. Idle Supply Current vs. VCC, Device Clocked by External 32kHz Crystal IDLE SUPPLY CURRENT vs. Vcc DEVICE CLOCKED BY 32KHz CRYSTAL 30 25 I cc(µΑ) 20 15 10 TA = 85˚C TA = 25˚C 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc(V) Analog Comparator offset voltage is measured as absolute offset. Figure 61. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs.
ATtiny11/12 Figure 62. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V 10 TA = 25˚C Offset Voltage (mV) 8 6 TA = 85˚C 4 2 0 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Figure 63. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT VCC = 6V TA = 25˚C 60 50 I ACLK (nA) 40 30 20 10 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.
Figure 64. Calibrated RC Oscillator Frequency vs. VCC CALIBRATED RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1.22 TA = 25˚C TA = 45˚C TA = 70˚C 1.2 1.18 TA = 85˚C FRC(MHz) 1.16 1.14 1.12 1.1 1.08 1.06 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC(V) Figure 65. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. Vcc 1600 1400 TA = 25˚C 1200 TA = 85˚C FRC (kHz) 1000 800 600 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATtiny11/12 Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 66. Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 120 TA = 25˚C 100 TA = 85˚C I OP (µA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 Figure 67. Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 30 TA = 25˚C 25 TA = 85˚C IOP (µA) 20 15 10 5 0 0 0.5 1 1.5 2 2.
Figure 68. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) 70 TA = 25˚C 60 TA = 85˚C 50 I OL (mA) 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOL (V) Figure 69. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 20 TA = 25˚C 18 16 TA = 85˚C 14 I OH (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATtiny11/12 Figure 70. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) 25 TA = 25˚C 20 TA = 85˚C I OL (mA) 15 10 5 0 0 0.5 1 1.5 2 VOL (V) Figure 71. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) 6 TA = 25˚C 5 TA = 85˚C I OH (mA) 4 3 2 1 0 0 0.5 1 1.5 2 2.
Figure 72. I/O Pin Input Threshold Voltage vs. VCC (TA = 25°C) 2.5 Threshold Voltage (V) 2 1.5 1 0.5 0 2.7 4.0 5.0 VCC Figure 73. I/O Pin Input Hysteresis vs. VCC (TA = 25°C) 0.18 Input Hysteresis (V) 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 5.
ATtiny11/12 Register Summary ATtiny11 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F SREG I T H S V N Z C page 14 $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - INT0 PCIE - - - - - page 25 $3A GIFR - INTF0 PCIF - - - - - page 26 $39 TIMSK - - - - - - TOIE0 - page 26 $38 TIFR - - - - - - TOV0 - page 27 $37 Reserved $36 Reserved $35 MCUCR - - SE SM - - ISC01 ISC00 page 29 $34 MCUSR - - - - -
Register Summary ATtiny12 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $3F SREG I T H S V N Z C page 14 $3E Reserved $3D Reserved $3C Reserved $3B GIMSK - INT0 PCIE - - - - - page 25 $3A GIFR - INTF0 PCIF - - - - - page 26 $39 TIMSK - - - - - - TOIE0 - page 26 $38 TIFR - - - - - - TOV0 - page 27 $37 Reserved $36 Reserved $35 MCUCR - PUD SE SM - - ISC01 ISC00 page 29 $34 MCUSR - - - - WDRF BORF
ATtiny11/12 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with C
Instruction Set Summary (Continued) Mnemonics Operands Description Operation Flags #Clocks DATA TRANSFER INSTRUCTIONS LD Rd,Z Load Register Indirect Rd ← (Z) None 2 ST Z,Rr Store Register Indirect (Z) ← Rr None 2 MOV Rd, Rr Move Between Registers Rd ← Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 Load Program Memory R0 ← (Z) None 3 2 LPM BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Regi
ATtiny11/12 Ordering Information Power Supply Speed (MHz) Ordering Code Package 2.7 - 5.
Packaging Information 8P3 E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL MIN NOM A b2 b3 b 4 PLCS Side View L 0.210 NOTE 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 6 b3 0.030 0.039 0.045 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 3 3 0.100 BSC eA L Notes: MAX 0.300 BSC 0.115 0.130 4 0.150 2 1.
ATtiny11/12 8S2 1 H N Top View e b A D COMMON DIMENSIONS (Unit of Measure = mm) Side View SYMBOL A C A1 L E End View NOM MAX NOTE 2.03 A1 0.05 0.33 b 0.35 0.51 5 C 0.18 0.25 5 D 5.13 5.38 E 5.13 5.41 H 7.62 8.38 L 0.51 0.89 e Notes: 1. 2. 3. 4. 5. MIN 1.78 1.27 BSC 2, 3 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included.
Data Sheet Change Log for ATtiny11/12 Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 1006C-09/01 to Rev. 1006D-07/03 1. Updated VBOT values in Table 8 on page 19.
ATtiny11/12 Table of Contents Features................................................................................................. 1 Pin Configuration.................................................................................. 1 Description ............................................................................................ 2 ATtiny11 Block Diagram ....................................................................................... ATtiny12 Block Diagram ..............................
High-voltage Serial Programming Algorithm....................................................... High-voltage Serial Programming Characteristics .............................................. Low-voltage Serial Downloading (ATtiny12 only) ............................................... Low-voltage Serial Programming Characteristics ............................................... 49 52 52 56 Electrical Characteristics...................................................................
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