Datasheet

4. Block Diagram
Figure 4-1. Block Diagram
CPU
ADC[7:0]
Vcc
I/O
PORTS
D
A
T
A
B
U
S
SRAM
FLASH
AC
AIN0
AIN1
ACO
ADCMUX
Watchdog
Timer
Power
management
and clock
control
Vcc
GND
Power
Supervision
POR & RESET
RESET
PCINT[9:0]
INT0
USART 0
RxD0
TxD0
XCK0
Interrupt
Clock generation
128 kHz Internal Osc
External clock
8MHz Calib Osc
PA[7:0]
PB[3:0]
Internal
Reference
ADC
TC 0
(16-bit)
OC0A/B
T0
ICP0
Atmel ATtiny102/ATtiny104 [DATASHEET]
Atmel-42505A-8-bit AVR Microcontroller_Datasheet_Preliminary Summary-02/2016
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