Datasheet

6. I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions. The following table describes the peripheral signals
multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
14-pin 8-pin Pin name Special INT
(2)
ADC
(2)
AC USART Timer Programming
(7)
1 1 V
CC
2 2 PA[0]
(1)
CLKI PCINT0 ADC0 AIN0 T0 TPICLK
3 3 PA[1]
(4)
PCINT1 ADC1 AIN1 OC0B TPIDATA
4 4 PA[2] RESET PCINT2 RESET
5 - PA[3]
(8)
PCINT3 OC0A
6 - PA[4]
(8)
PCINT4 ICP0
7 - PA[5]
(4)(8)
PCINT5 ADC2 OC0B
8 - PA[6] PCINT6 ADC3
9 - PA[7] PCINT7
10 - PB[0] PCINT8 ADC4
11 5 PB[1]
(5)
CLKO PCINT9/INT0 ADC5 XCK0 OC0A
12 6 PB[2]
(6)
PCINT10 ADC6 TxD0 ICP0
13 7 PB[3]
(3)(8)
PCINT11 ADC7 ACO RxD0 T0
14 8 GND
Note:
1. Priority of CLKI is higher than ADC0. When EXT_CLK is enabled, ADC channel will not work and
DIDR0 will not disable the digital input buffer.
2. When both PCINT and the corresponding ADC channel are enabled, the digital input buffer will not
be disabled.
3. When ACO is enabled, ADC, TC and USART RX inputs are not disabled.
4. When OC0B is enabled, ADC and AC will continue to receive inputs on that channel if enabled.
5. When CLKO is enable in PB[1], OCA will get lower priority.
6. When USART is enabled, the users must ensure that ADC channel corresponding to the TxD0 pin
is not used. Because DIDR0 register will only control the input buffer, not the output part.
7. During reset/external programming, all pins are treated as inputs and outputs are disabled.
8. Alternative location when enabling T/C Remap
Atmel ATtiny102/ATtiny104 [DATASHEET]
Atmel-42505A-8-bit AVR Microcontroller_Datasheet_Preliminary Summary-02/2016
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