Datasheet

95
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
14. Programming interface
14.1 Features
• Physical Layer:
– Synchronous Data Transfer
– Bi-directional, Half-duplex Receiver And Transmitter
– Fixed Frame Format With One Start Bit, 8 Data Bits, One Parity Bit And 2 Stop Bits
– Parity Error Detection, Frame Error Detection And Break Character Detection
– Parity Generation And Collision Detection
– Automatic Guard Time Insertion Between Data Reception And Transmission
• Access Layer:
– Communication Based On Messages
– Automatic Exception Handling Mechanism
– Compact Instruction Set
– NVM Programming Access Control
– Tiny Programming Interface Control And Status Space Access Control
– Data Space Access Control
14.2 Overview
The Tiny Programming Interface (TPI) supports external programming of all Non-Volatile Memories (NVM). Mem-
ory programming is done via the NVM Controller, by executing NVM controller commands as described in “Memory
Programming” on page 106.
The Tiny Programming Interface (TPI) provides access to the programming facilities. The interface consists of two
layers: the access layer and the physical layer. The layers are illustrated in Figure 14-1.
Figure 14-1. The Tiny Programming Interface and Related Internal Interfaces
Programming is done via the physical interface. This is a 3-pin interface, which uses the RESET
pin as enable, the
TPICLK pin as the clock input, and the TPIDATA pin as data input and output.
NVM can be programmed at 5V, only.
14.3 Physical Layer of Tiny Programming Interface
The TPI physical layer handles the basic low-level serial communication. The TPI physical layer uses a bi-direc-
tional, half-duplex serial receiver and transmitter. The physical layer includes serial-to-parallel and parallel-to-serial
data conversion, start-of-frame detection, frame error detection, parity error detection, parity generation and colli-
sion detection.
ACCESS
LAYER
PHYSICAL
LAYER
NVM
CONTROLLER
NON-VOLATILE
MEMORIES
TPICLK
RESET
T
PIDATA
TINY PROGRAMMING INTERFACE (TPI)
DATA BUS