Datasheet

ATtiny4/5/9/10 [DATASHEET]

8127F–AVR–02/2013

13.12.4 ADCL – ADC Data Register

When an ADC conversion is complete, the result is found in the ADC register.

• Bits 7:0 – ADC7:0: ADC Conversion Result

These bits represent the result from the conversion.

13.12.5 DIDR0

– Digital Input Disable Register 0

• Bits 7:4 – Res: Reserved Bit

These bits are reserved and will always read zero.

• Bits 3:0 – ADC3D..ADC0D: ADC3..0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corre-

sponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the

ADC3..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power

consumption in the digital input buffer.

1 0 0 Timer/Counter 0 Overflow

1 0 1 Timer/Counter 0 Compare Match B

1 1 0 Pin Change Interrupt 0 Request

1 1 1 Timer/Counter 0 Capture Event

Table 13-4. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source

Bit 76543210

0x19 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

Read/WriteRRRRRRRR

Initial Value00000000

Bit 765432 1 0

0x17 – – – – ADC3D ADC2D ADC1D ADC0D DIDR0

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0