Datasheet

79
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to
zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting.
• Bit 0 – PSR: Prescaler 0 Reset Timer/Counter 0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hard-
ware, except if the TSM bit is set.