Datasheet

54
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
11.3 Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter control Regis-
ter B (TCCR0B). For details on clock sources and prescaler, see section “Prescaler”.
11.3.1 Prescaler
The Timer/Counter can be clocked directly by the system clock (by setting the CS2:0 = 1). This provides the fastest
operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f
CLK_I/O
). Alternatively,
one of four taps from the prescaler can be used as a clock source.
See Figure 11-2 for an illustration of the prescaler unit.
Figure 11-2. Prescaler for Timer/Counter0
Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 11-3 on page 55.
The prescaled clock has a frequency of f
CLK_I/O
/8, f
CLK_I/O
/64, f
CLK_I/O
/256, or f
CLK_I/O
/1024. See Table 11-6 on page
75 for details.
11.3.1.1 Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/CounterCounter,
and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter’s clock select,
the state of the prescaler will have implications for situations where a prescaled clock is used. One example of
prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (CS2:0 = 2, 3, 4, or 5). The num-
ber of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution.
PSR10
Clear
clk
T0
T0
clk
I/O
Synchronization