Datasheet

49
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
• PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source for pin change
interrupt 0.
• TPICLK: Serial Programming Clock.
• Port B, Bit 2 – ADC2/CLKO/INT0/PCINT2/T0
• ADC2: Analog to Digital Converter, Channel 2
(ATtiny5/10, only)
• CLKO: System Clock Output. The system clock can be output on pin PB2. The system clock will be output if
CKOUT bit is programmed, regardless of the PORTB2 and DDB2 settings.
• INT0: External Interrupt Request 0
• PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source for pin change
interrupt 0.
• T0: Timer/Counter0 counter source.
• Port B, Bit 3 – ADC3/PCINT3/RESET
• ADC3: Analog to Digital Converter, Channel 3 (ATtiny5/10, only)
• PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source for pin change
interrupt 0.
• RESET
:
Table 10-4 and Table 10-5 on page 50 relate the alternate functions of Port B to the overriding signals shown in
Figure 10-6 on page 46.
Table 10-4. Overriding Signals for Alternate Functions in PB3..PB2
Notes: 1. RSTDISBL is 1 when the configuration bit is “0” (Programmed).
2. CKOUT is 1 when the configuration bit is “0” (Programmed).
Signal
Name PB3/ADC3/RESET
/PCINT3 PB2/ADC2/INT0/T0/CLKO/PCINT2
PUOE RSTDISBL
(1)
CKOUT
(2)
PUOV 1 0
DDOE RSTDISBL
(1)
CKOUT
(2)
DDOV 0 1
PVOE 0 CKOUT
(2)
PVOV 0 (system clock)
PTOE 0 0
DIEOE
RSTDISBL
(1)
+ (PCINT3 • PCIE0) +
ADC3D
(PCINT2 • PCIE0) + ADC2D + INT0
DIEOV RSTDISBL • PCINT3 • PCIE0 (PCINT2 • PCIE0) + INT0
DI PCINT3 Input INT0/T0/PCINT2 Input
AIO ADC3 Input ADC2 Input