Datasheet

42
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to
be written logic zero.
Table 10-1 summarizes the control signals for the pin value.
Port pins are tri-stated when a reset condition becomes active, even when no clocks are running.
10.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI
instruction can be used to toggle one single bit in a port.
10.2.3 Break-Before-Make Switching
In Break-Before-Make mode, switching the DDRxn bit from input to output introduces an immediate tri-state period
lasting one system clock cycle, as indicated in Figure 10-3. For example, if the system clock is 4 MHz and the
DDRxn is written to make an output, an immediate tri-state period of 250 ns is introduced before the value of
PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system clock cycles. The
Break-Before-Make mode applies to the entire port and it is activated by the BBMx bit. For more details, see
“PORTCR – Port Control Register” on page 50.
When switching the DDRxn bit from output to input no immediate tri-state period is introduced.
Table 10-1. Port Pin Configurations
DDxn PORTxn PUExn I/O Pull-up Comment
0X
0
Input No Tri-state (hi-Z)
0X
1
Input Yes Sources current if pulled low externally
10
0
Output No Output low (sink)
10
1
Output Yes
NOT RECOMMENDED.
Output low (sink) and internal pull-up active.
Sources current through the internal pull-up
resistor and consumes power constantly
11
0
Output No Output high (source)
11
1
Output Yes Output high (source) and internal pull-up active