Datasheet

29
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
When VLM is active and voltage at V
CC
is above the selected trigger level operation will be as normal and the VLM
can be shut down for a short period of time. If voltage at V
CC
drops below the selected threshold the VLM will either
flag an interrupt or generate a reset, depending on the configuration.
When the VLM has been configured to generate a reset at low supply voltage it will keep the device in reset as long
as V
CC
is below the reset level. See Table 8-4 on page 34 for reset level details. If supply voltage rises above the
reset level the condition is removed and the MCU will come out of reset, and initiate the power-up start-up
sequence.
If supply voltage drops enough to trigger the POR then PORF is set after supply voltage has been restored.
8.2.3 External Reset
An External Reset is generated by a low level on the RESET
pin if enabled. Reset pulses longer than the minimum
pulse width (see section “System and Reset Characteristics” on page 118) will generate a reset, even if the clock is
not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset
Threshold Voltage – V
RST
– on its positive edge, the delay counter starts the MCU after the time-out period – t
TOUT
– has expired. External reset is ignored during Power-on start-up count. After Power-on reset the internal reset is
extended only if RESET pin is low when the initial Power-on delay count is complete. See Figure 8-2 and Figure 8-
3 on page 28.
Figure 8-4. External Reset During Operation
8.2.4 Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of
this pulse, the delay timer starts counting the time-out period t
TOUT
. See page 30 for details on operation of the
Watchdog Timer and Table 16-4 on page 118 for details on reset time-out.
CC