Datasheet

ATtiny4/5/9/10 [DATASHEET]

8127F–AVR–02/2013

6.5.3 CLKPSR – Clock Prescale Register

• Bits 7:4 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits

can be written at run-time to vary the clock frequency and suit the application requirements. As the prescaler

divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The

division factors are given in Table 6-4.

To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the

CLKPS bits:

1. Write the signature for change enable of protected I/O register to register CCP

2. Within four instruction cycles, write the desired value to CLKPS bits

At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has

a frequency higher than the maximum allowed the application software must make sure a sufficient division factor

is used. To make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler

settings.

Bit 76543210

0x36

– – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPSR

Read/Write R R R R R/W R/W R/W R/W

Initial Value00000011

Table 6-4. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1

0001 2

0010 4

0011 8 (default)

0100 16

0101 32

0110 64

0111 128

1000 256

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved