Datasheet

162
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
23. Datasheet Revision History
23.1 Rev. 8127F – 02/13
1. Updated:
Ordering information on page 152, page 153, page 154, and page 155
23.2 Rev. 8127E – 11/11
1. Updated:
Device status from Preliminary to Final
Ordering information on page 152, page 153, page 154, and page 155
23.3 Rev. 8127D – 02/10
1. Added UDFN package in “Features” on page 1, “Pin Configurations” on page 2, “Ordering Information” on
page 152, and in “Packaging Information” on page 156
2. Updated Figure 8-2 and Figure 8-3 in Section 8.2.1 “Power-on Reset” on page 27
3. Updated Section 8.2.3 “External Reset” on page 29
4. Updated Figures 17-36 and 17-51 in “Typical Characteristics”
5. Updated notes in Section 20. “Ordering Information” on pages 152 - 155
6. Added device Rev. E in Section 22. “Errata” on page 158
23.4 Rev. 8127C – 10/09
1. Updated values and notes:
Table 16-1 in Section 16.2 “DC Characteristics” on page 115
Table 16-3 in Section 16.4 “Clock Characteristics” on page 117
Table 16-6 in Section 16.5.2 “VCC Level Monitor” on page 118
Table 16-9 in Section 16.8 “Serial Programming Characteristics” on page 120
2. Updated Figure 16-1 in Section 16.3 “Speed” on page 116
3. Added Typical Characteristics Figure 17-36 in Section 17.8 “Analog Comparator Offset” on page 139.
Also, updated some other plots in Typical Characteristics.
4. Added topside and bottomside marking notes in Section 20. “Ordering Information” on page 152, up to
page 155
5. Added ESD errata, see Section 22. “Errata” on page 158
6. Added Lock bits re-programming errata, see Section 22. “Errata” on page 158
23.5 Rev. 8127B – 08/09
1. Updated document template
2. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny9
3. Added section:
“Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10” on page 4
4. Updated sections:
“ADC Clock – clkADC” on page 18
“Starting from Idle / ADC Noise Reduction / Standby Mode” on page 20
“ADC Noise Reduction Mode” on page 24
“Analog to Digital Converter” on page 25