Datasheet

101
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
14.5.1 SLD - Serial LoaD from data space using indirect addressing
The SLD instruction uses indirect addressing to load data from the data space to the TPI physical layer shift-regis-
ter for serial read-out. The data space location is pointed by the Pointer Register (PR), where the address must
have been stored before data is accessed. The Pointer Register is either left unchanged by the operation, or post-
incremented, as shown in Table 14-2.
14.5.2 SST - Serial STore to data space using indirect addressing
The SST instruction uses indirect addressing to store into data space the byte that is shifted into the physical layer
shift register. The data space location is pointed by the Pointer Register (PR), where the address must have been
stored before the operation. The Pointer Register can be either left unchanged by the operation, or it can be post-
incremented, as shown in Table 14-3.
14.5.3 SSTPR - Serial STore to Pointer Register
The SSTPR instruction stores the data byte that is shifted into the physical layer shift register to the Pointer Regis-
ter (PR). The address bit of the instruction specifies which byte of the Pointer Register is accessed, as shown in
Table 14-4.
SLDCS data, a
Serial LoaD from Control and Status space
using direct addressing
data  CSS[a]
SSTCS a, data
Serial STore to Control and Status space
using direct addressing
CSS[a]
 data
SKEY Key, {8{data}} Serial KEY Key
 {8{data}}
Table 14-1. Instruction Set Summary (Continued)
Mnemonic Operand Description Operation
Table 14-2. The Serial Load from Data Space (SLD) Instruction
Operation Opcode Remarks Register
data  DS[PR]
0010 0000
PR  PR
Unchanged
data
 DS[PR]
0010 0100
PR  PR + 1
Post increment
Table 14-3. The Serial Store to Data Space (SLD) Instruction
Operation Opcode Remarks Register
DS[PR] data
0110 0000
PR  PR
Unchanged
DS[PR]
data
0110 0100
PR  PR + 1
Post increment
Table 14-4. The Serial Store to Pointer Register (SSTPR) Instruction
Operation Opcode Remarks
PR[a] data
0110 100a Bit ‘a’ addresses Pointer Register byte