Atmel 8-bit AVR Microcontroller with 512/1024 Bytes In-System Programmable Flash ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 54 Powerful Instructions – Most Single Clock Cycle Execution – 16 x 8 General Purpose Working Registers – Fully Static Operation – Up to 12 MIPS Throughput at 12 MHz Non-volatile Program and Data Memories – 512/1024 Bytes of In-System Programmable Flash Program Memory –
1. Pin Configurations Figure 1-1. Pinout of ATtiny4/5/9/10 SOT-23 (PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0 GND (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 1 2 3 6 5 4 PB3 (RESET/PCINT3/ADC3) VCC PB2 (T0/CLKO/PCINT2/INT0/ADC2) UDFN (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 NC NC GND 1 2 3 4 8 7 6 5 PB2 (T0/CLKO/PCINT2/INT0/ADC2) VCC PB3 (RESET/PCINT3/ADC3) PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0) 1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3..
2. Overview ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure 2-1.
channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and four software selectable power saving modes. ATtiny5/10 are also equipped with a fourchannel, 8-bit Analog to Digital Converter (ADC). Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and interrupt system to continue functioning.
3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/microcontroller/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 4-1.
Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register.
Figure 4-2 below shows the structure of the 16 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers 7 0 R16 R17 Note: General R18 Purpose … Working R26 X-register Low Byte Registers R27 X-register High Byte R28 Y-register Low Byte R29 Y-register High Byte R30 Z-register Low Byte R31 Z-register High Byte A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny4/5/9/10 implement only 16 registers.
In different addressing modes these address registers function as automatic increment and automatic decrement (see document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack.
Figure 4-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the program memory space.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) Note: 4.7.1 See “Code Examples” on page 5. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum.
4.8.2 SPH and SPL — Stack Pointer Register Bit 4.8.
• Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information.
5. Memories This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the program memory space and the data memory space. 5.1 In-System Re-programmable Flash Program Memory The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles.
Figure 5-1. Data Memory Map (Byte Addressing) I/O SPACE 0x0000 ... 0x003F SRAM DATA MEMORY 0x0040 ... 0x005F (reserved) 0x0060 ... 0x3EFF NVM LOCK BITS 0x3F00 ... 0x3F01 (reserved) 0x3F02 ... 0x3F3F CONFIGURATION BITS 0x3F40 ... 0x3F41 (reserved) 0x3F42 ... 0x3F7F CALIBRATION BITS 0x3F80 ... 0x3F81 (reserved) 0x3F82 ... 0x3FBF DEVICE ID BITS 0x3FC0 ... 0x3FC3 (reserved) 0x3FC4 ... 0x3FFF FLASH PROGRAM MEMORY (reserved) 0x4400 ...
5.3 I/O Memory The I/O space definition of the ATtiny4/5/9/10 is shown in “Register Summary” on page 148. All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between the 16 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
6. Clock System Figure 6-1 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 23. The clock systems is detailed below. Figure 6-1.
6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. The ADC is available in ATtiny5/10, only. 6.2 Clock Sources All synchronous clock signals are derived from the main clock.
6.2.3 Internal 128 kHz Oscillator The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The frequency depends on supply voltage, temperature and batch variations. This clock may be select as the main clock by setting the CLKMS[1:0] bits in CLKMSR to 0b01. 6.2.4 Switching Clock Source The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings Register” on page 21.
6.4 Starting 6.4.1 Starting from Reset The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps, as follows. 1. The first step after the reset source has been released consists of the device counting the reset start-up time. The purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels.
6.5 Register Description 6.5.1 CLKMSR – Clock Main Settings Register Bit 7 6 5 4 3 2 1 0 0x37 – – – – – – CLKMS1 CLKMS0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 CLKMSR • Bit 7:2 – Res: Reserved Bits These bits are reserved and always read zero. • Bit 1:0 – CLKMS[1:0]: Clock Main Select Bits These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock.
6.5.3 CLKPSR – Clock Prescale Register Bit 7 6 5 4 3 2 1 0 0x36 – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 1 1 CLKPSR • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock.
7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
7.1.2 ADC Noise Reduction Mode When bits SM2:0 are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkNVM, while allowing the other clocks to run. This mode improves the noise environment for the ADC, enabling higher resolution measurements.
7.3.2 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. See “Analog to Digital Converter” on page 82 for details on ADC operation. The ADC is available in ATtiny5/10, only. 7.3.3 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off.
Table 7-2. Note: Sleep Mode Select SM2 SM1 SM0 Sleep Mode 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 1. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.
8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after VCC rise. The reset signal is activated again, without any delay, when VCC decreases below the detection level. Figure 8-2. MCU Start-up, RESET Tied to VCC V CC V POT RESET V RST TIME-OUT t TOUT INTERNAL RESET Figure 8-3.
When VLM is active and voltage at VCC is above the selected trigger level operation will be as normal and the VLM can be shut down for a short period of time. If voltage at VCC drops below the selected threshold the VLM will either flag an interrupt or generate a reset, depending on the configuration. When the VLM has been configured to generate a reset at low supply voltage it will keep the device in reset as long as VCC is below the reset level. See Table 8-4 on page 34 for reset level details.
Figure 8-5. Watchdog Reset During Operation CC CK Watchdog Timer The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. See Figure 8-6. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-2 on page 32. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs.
Table 8-1. WDT Configuration as a Function of the Fuse Settings of WDTON Safety Level WDTON WDT Initial State How to Disable the WDT How to Change Time-out Unprogrammed 1 Disabled Protected change sequence No limitations Programmed 2 Enabled Always enabled Protected change sequence 8.3.1 Procedure for Changing the Watchdog Timer Configuration The sequence for changing configuration differs between the two safety levels, as follows: 8.3.1.
8.4 8.4.1 Register Description WDTCSR – Watchdog Timer Control and Status Register Bit 7 6 5 4 3 2 1 0 WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 0x31 WDTCSR • Bit 7 – WDIF: Watchdog Timer Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
• Bits 5, 2:0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 8-3 on page 33. Table 8-3. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
Table 8-4. Setting the Trigger Level of Voltage Level Monitor. VLM2:0 Label Description 000 VLM0 Voltage Level Monitor disabled 001 VLM1L 010 VLM1H Triggering generates a regular Power-On Reset (POR). The VLM flag is not set 011 VLM2 100 VLM3 Triggering sets the VLM Flag (VLMF) and generates a VLM interrupt, if enabled 101 110 Not allowed 111 For VLM voltage levels, see Table 16-6 on page 118. 8.4.
9. Interrupts This section describes the specifics of the interrupt handling in ATtiny4/5/9/10. For a general explanation of the AVR interrupt handling, see “Reset and Interrupt Handling” on page 10. 9.1 Interrupt Vectors Interrupt vectors of ATtiny4/5/9/10 are described in Table 9-1 below. Table 9-1. Reset and Interrupt Vectors Vector No.
9.2 0x000B RESET: ldi 0x000C out SPH,r16 r16, high(RAMEND); Main program start 0x000D ldi r16, low(RAMEND) ; to top of RAM 0x000E out SPL,r16 0x000F sei 0x0010 ... ... ; Set Stack Pointer ; Enable interrupts External Interrupts External Interrupts are triggered by the INT0 pin or any of the PCINT3..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT3..0 pins are configured as outputs.
Figure 9-1. Timing of pin change interrupts pin_lat PCINT(0) D pcint_in_(0) Q clk 0 pcint_syn pcint_setflag PCIF pin_sync LE x PCINT(0) in PCMSK(x) clk clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF 9.3 Register Description 9.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 9-2. 9.3.2 Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.
9.3.4 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 0x12 – – – – – – – PCIE0 Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 PCICR • Bits 7:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT3..
10. I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors. Each output buffer has symmetrical drive characteristics with both high sink and source capability.
10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) REx Q D PUExn Q CLR RESET Q WEx D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx SLEEP WPx RRx SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O SLEEP: clk I/O : Note: 10.2.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to be written logic zero. Table 10-1 summarizes the control signals for the pin value. Table 10-1.
Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode SYSTEM CLK r16 0x02 r17 0x01 INSTRUCTIONS out DDRx, r16 nop PORTx DDRx 0x55 0x02 0x01 Px0 Px1 out DDRx, r17 0x01 tri-state tri-state tri-state intermediate tri-state cycle 10.2.4 intermediate tri-state cycle Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit.
Figure 10-5. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd 10.2.5 Digital Input Enable and Sleep Modes As shown in Figure 10-2 on page 41, the digital input signal can be clamped to ground at the input of the schmitttrigger.
10.2.7 Program Example The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from 2 to 3 as input with a pull-up assigned to port pin 2. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example ...
Figure 10-6.
Table 10-2 on page 47 summarizes the function of the overriding signals. The pin and port indexes from Figure 106 on page 46 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
10.3.1 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-3 on page 48. Table 10-3.
• PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source for pin change interrupt 0. • TPICLK: Serial Programming Clock. • Port B, Bit 2 – ADC2/CLKO/INT0/PCINT2/T0 • ADC2: Analog to Digital Converter, Channel 2 (ATtiny5/10, only) • CLKO: System Clock Output. The system clock can be output on pin PB2. The system clock will be output if CKOUT bit is programmed, regardless of the PORTB2 and DDB2 settings.
Table 10-5. Signal Name PB1/ADC1/AIN1/OC0B/CLKI/ICP0/PCINT1 PUOE EXT_CLOCK 0 PUOV 0 0 DDOE EXT_CLOCK(1) 0 DDOV 0 0 EXT_CLOCK (1) + OC0B Enable OC0A Enable PVOV EXT_CLOCK (1) • OC0B OC0A PTOE 0 0 (1) + (PCINT1 • PCIE0) + DIEOE EXT_CLOCK ADC1D DIEOV (EXT_CLOCK(1) • PWR_DOWN) + (EXT_CLOCK(1) • PCINT1 • PCIE0) PCINT0 • PCIE0 DI CLOCK/ICP0/PCINT1 Input PCINT0 Input AIO ADC1/Analog Comparator Negative Input ADC0/Analog Comparator Positive Input Notes: 10.4.
10.4.3 10.4.4 10.4.
11. 16-bit Timer/Counter0 Features • • • • • • • • • • • 11.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 11-1 on page 52. For actual placement of I/O pins, refer to “Pinout of ATtiny4/5/9/10” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 72. Most register and bit references in this section are written in general form.
11.3 Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter control Register B (TCCR0B). For details on clock sources and prescaler, see section “Prescaler”. 11.3.1 Prescaler The Timer/Counter can be clocked directly by the system clock (by setting the CS2:0 = 1).
11.3.2 External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 11-3 on page 55 shows a functional equivalent block diagram of the T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O).
Count Direction Clear clkT0 TOP BOTTOM Increment or decrement TCNT0 by 1. Select between increment and decrement. Clear TCNT0 (set all bits to zero). Timer/Counter clock. Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT0H) containing the upper eight bits of the counter, and Counter Low (TCNT0L) containing the lower eight bits.
Figure 11-5. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) WRITE ICRnL (8-bit) TCNTnH (8-bit) ICRn (16-bit Register) ACO* Analog Comparator ACIC* TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Canceler Edge Detector ICFn (Int.Req.
clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR0 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP0 pin. 11.5.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme.
Figure 11-6. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCR0x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
11.6.2 Compare Match Blocking by TCNT0 Write All CPU writes to the TCNT0 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 11.6.
Figure 11-7. Compare Match Output Unit, Schematic (non-PWM Mode) COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared or toggle at a compare match (“Compare Match Output Unit” on page 60) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 69. 11.8.1 Normal Mode The simplest mode of operation is the Normal mode (WGM03:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed.
not desirable. An alternative will then be to use the fast PWM mode using OCR0A for defining TOP (WGM03:0 = 15) since the OCR0A then will be double buffered. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC0A = 1).
Figure 11-9. Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. In addition the OC0A or ICF0 flag is set at the same timer clock cycle as TOV0 is set when either OCR0A or ICR0 is used for defining the TOP value.
The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ----------------------------------N 1 + TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle.
Figure 11-10. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM.
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR0x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 11.8.
Figure 11-11. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV0) is set at the same timer clock cycle as the OCR0x Registers are updated with the double buffer value (at BOTTOM).
The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 11.
TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV0 flag at BOTTOM. Figure 11-14. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 11-15 on page 70 shows the same timing data, but with the prescaler enabled.
read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR0A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte.
The code example returns the TCNT0 value in the r17:r16 register pair. The following code example shows how to do an atomic write of the TCNT0 Register contents. Writing any of the OCR0A/B or ICR0 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT0: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT0 to r17:r16 out TCNT0H,r17 out TCNT0L,r16 ; Restore global interrupt flag out SREG,r18 ret Note: See “Code Examples” on page 5.
When OC0A or OC0B is connected to the pin, the function of COM0x1:0 bits depends on the WGM03:0 bits. Table 11-2 shows the COM0x1:0 bit functionality when the WGM03:0 bits are set to a Normal or CTC (non-PWM) Mode. Table 11-2.
ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (“Modes of Operation” on page 61). Table 11-5. 11.11.
When the ICR0 is used as TOP value (see description of the WGM03:0 bits located in the TCCR0A and the TCCR0B Register), the ICP0 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR0B is written. • Bits 4:3 – WGM03:2: Waveform Generation Mode See “TCCR0A – Timer/Counter0 Control Register A” on page 72.
• Bits 5:0 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when the register is written. 11.11.
11.11.7 ICR0H and ICR0L – Input Capture Register 0 Bit 7 6 5 4 3 0x23 ICR0[15:8] 0x22 ICR0[7:0] 2 1 0 ICR0H ICR0L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT0) value each time an event occurs on the ICP0 pin (or optionally on the Analog Comparator output for Timer/Counter0). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size.
11.11.9 TIFR0 – Timer/Counter Interrupt Flag Register 0 Bit 7 6 5 4 3 2 1 0 0x2A – – ICF0 – – OCF0B OCF0A TOV0 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR0 • Bits 7:6, 4:3 – Reserved Bits These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to zero when the register is written.
is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR bit is cleared by hardware, and the Timer/Counter start counting. • Bit 0 – PSR: Prescaler 0 Reset Timer/Counter 0 When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.
12. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 12-1.
• Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
13. Analog to Digital Converter 13.1 Features • • • • • • • • • • • • 13.2 8-bit Resolution 0.5 LSB Integral Non-linearity ± 1 LSB Absolute Accuracy 65µs Conversion Time 15 kSPS at Full Resolution Four Multiplexed Single Ended Input Channels Input Voltage Range: 0 – VCC Supply Voltage Range: 2.5V – 5.
Figure 13-1. Analog to Digital Converter Block Schematic ADCSRB ADCL ADIE ADEN ADPS0 ADPS1 ADPS2 ADSC ADATE ADCSRA ADTS2:0 ADC IRQ TRIGGER SELECT PRESCALER ADIF CHANNEL START DECODER ADC7:0 MUX1 MUX0 ADMUX INTERRUPT FLAGS 8-BIT DATA BUS CONVERSION LOGIC VREF VCC 8-BIT DAC + ADC3 ADC2 ADC1 INPUT MUX SAMPLE & HOLD COMPARATOR ADC0 13.
Figure 13-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER CLKADC START ADIF ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC data register. The first conversion must be started by writing a logical one to bit ADSC bit in ADCSRA.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles, as summarised in Table 13-1 on page 86. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. See Figure 13-4. Figure 13-4.
Figure 13-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCL Conversion Result Prescaler MUX Reset Update Conversion Prescaler Reset Complete Sample & Hold In Free Running mode (see Figure 13-7), a new conversion will be started immediately after the conversion completes, while ADSC remains high. Figure 13-7.
13.6 Changing Channel The MUXn bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channel selection only takes place at a safe point during the conversion. The channel is continuously updated until a conversion is started. Once the conversion starts, the channel selection is locked to ensure a sufficient sampling time for the ADC.
be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption. 13.
Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as described in Section 13.7 on page 87. A good system design with properly placed, external bypass capacitors does reduce the need for using ADC Noise Reduction Mode 13.10 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0xFE to 0xFF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 13-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 13-11.
Figure 13-12. Differential Non-linearity (DNL) Output Code 0xFF 1 LSB DNL 0x00 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
13.12 Register Description 13.12.1 ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 0x1B – – – – – – MUX1 MUX0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bits 7:2 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 1:0 – MUX1:0: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. See Table 13-2 for details.. Table 13-2.
• Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is requested if the ADIE bit is set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one, the ADC Conversion Complete Interrupt request is enabled.
Table 13-4. 13.12.
14. Programming interface 14.
The TPI is accessed via three pins, as follows: RESET: TPICLK: TPIDATA: Tiny Programming Interface enable input Tiny Programming Interface clock input Tiny Programming Interface data input/output In addition, the VCC and GND pins must be connected between the external programmer and the device. See Figure 14-2. Figure 14-2.
14.3.2 Disabling Provided that the NVM enable bit has been cleared, the TPI is automatically disabled if the RESET pin is released to inactive high state or, alternatively, if VHV is no longer applied to the RESET pin. If the NVM enable bit is not cleared a power down is required to exit TPI programming mode. See NVMEN bit in “TPISR – Tiny Programming Interface Status Register” on page 105. 14.3.3 Frame Format The TPI physical layer supports a fixed frame format.
Figure 14-6. Data changing and Data sampling. TPICLK TPIDATA SAMPLE SETUP The TPI physical layer supports two modes of operation: Transmit and Receive. By default, the layer is in Receive mode, waiting for a start bit. The mode of operation is controlled by the access layer. 14.3.7 Serial Data Reception When the TPI physical layer is in receive mode, data reception is started as soon as a start bit has been detected.
The collision detection is enabled in transmit mode, when the output driver has been disabled. The data line should now be kept high by the internal pull-up and it is monitored to see, if it is driven low by the external programmer. If the output is read low, a collision has been detected. There are some potential pit-falls related to the way collision detection is performed.
• Read messages. A read message is a request to read data. The TPI reacts to the request by sending the byte operands. This message type is used with the SLDCS, SLD and SIN instructions. All the instructions except the SKEY instruction require the instruction to be followed by one byte operand. The SKEY instruction requires 8 byte operands. For more information, see the TPI instruction set on page 100. 14.4.
Table 14-1. 14.5.1 Mnemonic Operand Description Operation SLDCS data, a Serial LoaD from Control and Status space using direct addressing data CSS[a] SSTCS a, data Serial STore to Control and Status space using direct addressing CSS[a] data SKEY Key, {8{data}} Serial KEY Key {8{data}} SLD - Serial LoaD from data space using indirect addressing The SLD instruction uses indirect addressing to load data from the data space to the TPI physical layer shift-register for serial read-out.
14.5.4 SIN - Serial IN from i/o space using direct addressing The SIN instruction loads data byte from the I/O space to the shift register of the physical layer for serial read-out. The instuction uses direct addressing, the address consisting of the 6 address bits of the instruction, as shown in Table 14-5. Table 14-5. 14.5.
14.5.8 SKEY - Serial KEY signaling The SKEY instruction is used to signal the activation key that enables NVM programming. The SKEY instruction is followed by the 8 data bytes that includes the activation key, as shown in Table 14-9. Table 14-9. 14.6 The Serial KEY signaling (SKEY) Instruction Operation Opcode Remarks Key {8[data}} 1110 0000 Data bytes follow after instruction Accessing the Non-Volatile Memory Controller By default, NVM programming is not enabled.
14.7.1 TPIIR – Tiny Programming Interface Identification Register Bit 7 6 5 CSS: 0x0F 4 3 2 1 0 Programming Interface Identification Code TPIIR Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bits 7:0 – TPIIC: Tiny Programming Interface Identification Code These bits give the identification code for the Tiny Programming Interface. The code can be used be the external programmer to identify the TPI.
14.7.3 TPISR – Tiny Programming Interface Status Register Bit 7 6 5 4 3 2 1 CSS: 0x00 – – – – – – NVMEN 0 – Read/Write R R R R R R R/W R Initial Value 0 0 0 0 0 0 0 0 TPIPCR • Bits 7:2, 0 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 1 – NVMEN: Non-Volatile Memory Programming Enabled NVM programming is enabled when this bit is set. The external programmer can poll this bit to verify the interface has been successfully enabled.
15. Memory Programming 15.1 Features • Two Embedded Non-Volatile Memories: • • • • • 15.
15.3.1 Non-Volatile Memory Lock Bits The ATtiny4/5/9/10 provide two Lock Bits, as shown in Table 15-1. Table 15-1.
Notes: 1. This section is read-only. Table 15-4. Number of Words and Pages in the Flash (ATtiny4/5) Section Size (Bytes) Page Size (Words) Pages WADDR PADDR 512 8 32 [3:1] [9:4] 8 8 1 [3:1] – 16 8 2 [3:1] [4:4] 8 8 1 [3:1] – Code (program memory) Configuration Signature (1) Calibration (1) Notes: 15.3.3 1. This section is read-only. Configuration Section ATtiny4/5/9/10 have one configuration byte, which resides in the configuration section. See Table 15-5. Table 15-5.
15.3.4 Signature Section The signature section is a dedicated memory area used for storing miscellaneous device information, such as the device signature. Most of this memory section is reserved for internal use, as shown in Table 15-7. Table 15-7. Signature bytes Signature word data Signature word address High byte Low byte 0x00 Device ID 1 Manufacturer ID 0x01 Reserved for internal use Device ID 2 0x02 ...
When the NVM Controller is busy performing an operation it will signal this via the NVM Busy Flag in the NVM Control and Status Register. See “NVMCSR - Non-Volatile Memory Control and Status Register” on page 114. The NVM Command Register is blocked for write access as long as the busy flag is active. This is to ensure that the current command is fully executed before a new command can start.
15.4.3 Programming the Flash The Flash can be written word-by-word. Before writing a Flash word, the Flash target location must be erased. Writing to an un-erased Flash word will corrupt its content. The Flash is word-accessed for writing, and the data space uses byte-addressing to access Flash that has been mapped to data memory. It is therefore important to write the word in the correct order to the Flash, namely low bytes before high bytes. First, the low byte is written to the temporary buffer.
15.4.3.4 Erasing the Configuration Section The algorithm for erasing the Configuration section is as follows: 1. Write the SECTION_ERASE command to the NVMCMD register 2. Start the erase operation by writing a dummy byte to the high byte of any word location inside the configuration section 3. Wait until the NVMBSY bit has been cleared 15.4.3.5 Writing a Configuration Word The algorithm for writing a Configuration word is as follows. 1. Write the WORD_WRITE command to the NVMCMD register 2.
Refer to the Tiny Programming Interface description on page 95 for more detailed information of enabling the TPI and programming the NVM. 15.6.2 Exiting External Programming Mode Clear the NVM enable bit to disable NVM programming, then release the RESET pin. See NVMEN bit in “TPISR – Tiny Programming Interface Status Register” on page 105.
15.7 15.7.1 Register Description NVMCSR - Non-Volatile Memory Control and Status Register Bit 7 6 5 4 3 2 1 NVMBSY – – – – – – – Read/Write R/W R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0x32 0 NVMCSR • Bit 7 - NVMBSY: Non-Volatile Memory Busy This bit indicates the NVM memory (Flash memory and Lock Bits) is busy, being programmed. This bit is set when a program operation is started, and it remains set until the operation has been completed.
16. Electrical Characteristics 16.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Table 16-1. Symbol DC Characteristics. TA = -40C to +85C (Continued) Parameter Condition Power Supply Current(6) ICC Power-down mode(7) Notes: Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.2 0.5 mA Active 4MHz, VCC = 3V 0.8 1.2 mA Active 8MHz, VCC = 5V 2.7 4 mA Idle 1MHz, VCC = 2V 0.02 0.2 mA Idle 4MHz, VCC = 3V 0.13 0.5 mA Idle 8MHz, VCC = 5V 0.6 1.5 mA WDT enabled, VCC = 3V 4.5 10 µA WDT disabled, VCC = 3V 0.15 2 µA 1.
16.4 Clock Characteristics 16.4.1 Accuracy of Calibrated Internal Oscillator It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 17-39 on page 141 and Figure 17-40 on page 141. Table 16-2.
16.5 System and Reset Characteristics Table 16-4. Symbol Parameter VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin tTOUT Time-out after reset Note: 16.5.1 Reset, VLM, and Internal Voltage Characteristics Condition Min(1) Typ(1) 0.2 VCC VCC = 1.8V VCC = 3V VCC = 5V Max(1) Units 0.9VCC V 2000 700 400 32 ns 64 128 ms 1. Values are guidelines, only Power-On Reset Table 16-5. Symbol Characteristics of Enhanced Power-On Reset.
16.6 Analog Comparator Characteristics Table 16-7. Analog Comparator Characteristics, TA = -40C - 85C Symbol Parameter Condition VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 Digital Propagation Delay VCC = 1.8V - 5.5 1 tAPD tDPD 16.
16.8 Serial Programming Characteristics Figure 16-3. Serial Programming Timing Receive Mode Transmit Mode TPIDATA tIVCH tCHIX tCLOV TPICLK tCLCH tCHCL tCLCL Table 16-9.
17. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing.
Active Supply Current Figure 17-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0.7 5.5 V 0.6 5.0 V 0.5 4.5 V ICC (mA) 4.0 V 0.4 3.3 V 0.3 2.7 V 0.2 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 17-2. Active Supply Current vs. frequency (1 - 12 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 5 4.5 5.5 V 4 5.0 V 3.5 4.5 V 3 ICC (mA) 17.2 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.
Figure 17-3. Active Supply Current vs. VCC (Internal Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 8 MHz 3.5 -40 °C 25 °C 85 °C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-4. Active Supply Current vs. VCC (Internal Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 1 MHz 1 0.9 -40 °C 25 °C 85 °C 0.8 0.7 ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 17-5. Active Supply Current vs. VCC (Internal Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 128 KHz 0.12 -40 °C 25 °C 85 °C 0.1 ICC (mA) 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-6. Active Supply Current vs. VCC (External Clock, 32 kHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL OSCILLATOR, 32 KHz 0.04 -40 °C 85 °C 25 °C 0.035 0.03 ICC (mA) 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 17-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (PRR=0xFF) 0,1 0,09 5.5 V ICC (mA) 0,08 0,07 5.0 V 0,06 4.5 V 0,05 4.0 V 0,04 3.3 V 0,03 2.7 V 0,02 1.8 V 0,01 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 17-8. Idle Supply Current vs. Frequency (1 - 12 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (PRR=0xFF) 1 5.5 V 5.0 V 0,8 4.5 V 0,6 ICC (mA) 17.3 4.0 V 0,4 3.3 V 0,2 2.7 V 1.
Figure 17-9. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 0,7 85 °C 25 °C -40 °C 0,6 ICC (mA) 0,5 0,4 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 17-10. Idle Supply Current vs. VCC (Internal Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs.
Power-down Supply Current Figure 17-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 0.5 85 °C 0.45 0.4 0.35 ICC (uA) 0.3 0.25 0.2 0.15 25 °C 0.1 -40 °C 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 9 -40 °C 8 25 °C 85 °C 7 6 ICC (uA) 17.
Pin Pull-up Figure 17-13. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 60 50 IOP (uA) 40 30 20 10 25 °C 85 °C -40 °C 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) Figure 17-14. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 80 70 60 50 IOP (uA) 17.
Figure 17-15. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE 160 140 120 IOP (uA) 100 80 60 40 20 25 °C 85 °C -40 °C 0 0 1 2 3 4 5 6 VOP (V) Figure 17-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs.
Figure 17-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE 60 50 IRESET (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0,5 1 1 ,5 2,5 2 3 VRESET (V) Figure 17-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
Pin Driver Strength Figure 17-19. I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 1.8V 0.8 0.7 85 °C 0.6 VOL (V) 0.5 25 °C 0.4 -40 °C 0.3 0.2 0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOL (mA) Figure 17-20. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 0.8 0.7 85 °C 0.6 0.5 VOL (V) 17.6 25 °C -40 °C 0.4 0.3 0.2 0.
Figure 17-21. I/O pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 1 85 °C 0.8 -40 °C 25 °C VOL (V) 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 17-22. I/O Pin Output Voltage vs. Source Current (VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 1.8V 2 1.8 1.6 VOH (V) 1.4 1.2 -40 °C 1 25 °C 0.8 85 °C 0.6 0.4 0.2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 17-23. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.1 2.9 VOH (V) 2.7 2.5 -40 °C 25 °C 2.3 85 °C 2.1 1.9 1.7 1.5 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 17-24. I/O Pin output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5.2 5 VOH (V) 4.8 4.6 4.4 -40 °C 25 °C 4.
Figure 17-25. Reset Pin as I/O, Output Voltage vs. Sink Current OUTPUT VOLTAGE vs. SINK CURRENT RESET PIN AS I/O 1 3.0 V 1.8 V 0.9 0.8 0.7 5.0 V VOL (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 IOL (mA) Figure 17-26. Reset Pin as I/O, Output Voltage vs. Source Current OUTPUT VOLTAGE vs. SOURCE CURRENT RESET PIN AS I/O 5 4 VOH (V) 3 5.0 V 2 1 3.0 V 1.8 V 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin Threshold and Hysteresis Figure 17-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3,5 85 °C 25 °C -40 °C 3 Threshold (V) 2,5 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 17-28. I/O Pin Input threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 85 °C 25 °C -40 °C 2,5 2 Threshold (V) 17.
Figure 17-29. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 1 0,9 0,8 Input Hysteresis (V) 0,7 0,6 -40 °C 0,5 25 °C 0,4 85 °C 0,3 0,2 0,1 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 17-30. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) RESET PIN AS I/O THRESHOLD VOLTAGE vs.
Figure 17-31. Reset Pin as I/O, Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC VIL, RESET READ AS '0' 2,5 85 °C 25 °C -40 °C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 4,5 5 5,5 VCC (V) Figure 17-32. Reset Input Hysteresis vs. VCC (Reset Pin Used as I/O) RESET PIN AS I/O, INPUT HYSTERESIS vs.
Figure 17-33. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2,5 Threshold (V) 2 1,5 -40 °C 25 °C 1 85 °C 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 17-34. Reset Input Threshold Voltage vs. VCC (VIL, I/O pin Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs.
Figure 17-35. Reset Pin, Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 1 Input Hysteresis (V) 0,8 0,6 -40 °C 0,4 25 °C 85 °C 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Analog Comparator Offset Figure 17-36. Analog Comparator Offset ANALOG COMPARATOR OFFSET VCC = 5V 0.006 -40 0.004 Offset 17.8 25 0.
Internal Oscillator Speed Figure 17-37. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 110 109 108 Frequency (kHz) 107 -40 °C 106 105 25 °C 104 103 102 101 85 °C 100 99 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-38. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 110 109 108 107 Frequency (kHz) 17.9 106 105 104 1.8 V 103 2.7 V 102 3.3 V 101 4.0 V 5.
Figure 17-39. Calibrated Oscillator Frequency vs. VCC CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 8.4 -40 °C 8.2 Frequency (MHz) 25 °C 85 °C 8 7.8 7.6 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-40. Calibrated Oscillator Frequency vs. Temperature CALIBRATED 8.0MHz OSCILLATOR FREQUENCY vs. TEMPERATURE 8.3 8.2 Frequency (MHz) 8.1 8 7.9 5.0 V 7.8 3.0 V 7.7 1.8 V 7.
Figure 17-41. Calibrated Oscillator Frequency vs, OSCCAL Value CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE VCC = 3V 16 25 °C 85 °C -40 °C 14 Frequency (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 17.10 VLM Thresholds Figure 17-42. VLM1L Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 001 1.42 1.41 Threshold (V) 1.4 1.39 1.38 1.37 1.36 1.35 1.
Figure 17-43. VLM1H Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 010 1.7 Threshold (V) 1.65 1.6 1.55 1.5 1.45 1.4 -40 -20 0 20 40 60 80 100 60 80 100 Temperature (C) Figure 17-44. VLM2 Threshold of VCC Level Monitor VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 011 2.48 Threshold (V) 2.47 2.46 2.45 2.44 2.
Figure 17-45. VLM3 Threshold of VCC Level Monitorr2 VLM THRESHOLD vs. TEMPERATURE VLM2:0 = 100 3.9 Threshold (V) 3.8 3.7 3.6 3.5 3.4 -40 -20 0 20 40 60 80 100 Temperature (C) 17.11 Current Consumption of Peripheral Units Figure 17-46. ADC Current vs. VCC (ATtiny5/10, only) ADC CURRENT vs. VCC 4.0 MHz FREQUENCY 700 600 ICC (uA) 500 400 300 200 100 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 17-47. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 140 120 ICC (uA) 100 25 ˚C 80 60 40 20 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 17-48. VCC Level Monitor Current vs. VCC VLM SUPPLY CURRENT vs. VCC 0.35 0.3 VLM2:0 = 001 VLM2:0 = 010 VLM2:0 = 011 0.25 ICC (mA) VLM2:0 = 100 0.2 0.15 0.1 0.05 0 VLM2:0 = 000 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 17-49. Temperature Dependence of VLM Current vs. VCC VLM SUPPLY CURRENT vs. VCC VLM2:0 = 001 350 -40 °C 300 25 °C 85 °C ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 17-50. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs.
17.12 Current Consumption in Reset and Reset Pulsewidth Figure 17-51. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. VCC EXCLUDING CURRENT THROUGH THE RESET PULLUP 0,5 0,4 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V ICC (mA) 0,3 0,2 1.8 V 0,1 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Note: The default clock source for the device is always the internal 8 MHz oscillator.
18.
should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags.
19.
Mnemonics Operands Description Operation Flags #Clocks CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 1 1 SEC Set Carry C1 C CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I 0
20. Ordering Information 20.1 ATtiny4 Supply Voltage Speed (1) Temperature Package (2) Industrial (-40C to 85C) (4) 6ST1 ATtiny4-TSHR(5) 12 MHz 8MA4 ATtiny4-MAHR (6) 6ST1 ATtiny4-TS8R (5) 1.8 – 5.5V 10 MHz Notes: Extended (-40C to 125C) (6) Ordering Code (3) 1. For speed vs. supply voltage, see section 16.3 “Speed” on page 116. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS).
20.2 ATtiny5 Supply Voltage Speed (1) Temperature Package (2) Industrial (-40C to 85C) (4) 6ST1 ATtiny5-TSHR (5) 12 MHz 8MA4 ATtiny5-MAHR (6) 6ST1 ATtiny5-TS8R (5) 1.8 – 5.5V 10 MHz Notes: Extended (-40C to 125C) (6) Ordering Code (3) 1. For speed vs. supply voltage, see section 16.3 “Speed” on page 116. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3. Tape and reel. 4.
20.3 ATtiny9 Supply Voltage Speed (1) Temperature Package (2) Industrial (-40C to 85C) (4) 6ST1 ATtiny9-TSHR (5) 12 MHz 8MA4 ATtiny9-MAHR (6) 6ST1 ATtiny9-TS8R (5) 1.8 – 5.5V 10 MHz Notes: Extended (-40C to 125C) (6) Ordering Code (3) 1. For speed vs. supply voltage, see section 16.3 “Speed” on page 116. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3. Tape and reel. 4.
20.4 ATtiny10 Supply Voltage Speed (1) Temperature Package (2) Ordering Code (3) Industrial (-40C to 85C) (4) 6ST1 ATtiny10-TSHR (5) 12 MHz 8MA4 ATtiny10-MAHR (6) 6ST1 ATtiny10-TS8R (5) 1.8 – 5.5V 10 MHz Notes: Extended (-40C to 125C) (6) 1. For speed vs. supply voltage, see section 16.3 “Speed” on page 116. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish. 3. Tape and reel.
21. Packaging Information 21.1 6ST1 D 5 6 E E1 A 4 A2 Pin #1 ID A1 3 2 b 0.10 C SEATING PLANE A 1 A C Side View e Top View A2 A 0.10 C SEATING PLANE c 0.25 O C A1 C View A-A SEATING PLANE SEE VIEW B L View B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN Notes: 1. This package is compliant with JEDEC specification MO-178 Variation AB 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrustion or gate burrs shall not exceed 0.
21.2 8MA4 8 7 6 8x 5 0.05 c c 0.05 c E SIDE VIEW Pin 1 ID 1 2 3 4 D A1 TOP VIEW A D2 e 8 5 COMMON DIMENSIONS (Unit of Measure = mm) K E2 SYMBOL MIN NOM MAX A – – 0.60 A1 0.00 – 0.05 b 0.20 – 0.30 D 1.95 2.00 2.05 D2 1.40 1.50 1.60 E 1.95 2.00 2.05 E2 C0.2 4 1 L b BOTTOM VIEW 0.80 0.90 1.00 e – 0.50 – L 0.20 0.30 0.40 K 0.20 – – NOTE Note: 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES. 2.
22. Errata The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device. 22.1 ATtiny4 22.1.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.1.2 Rev. D • ESD HBM (ESD STM 5.
22.2 ATtiny5 22.2.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.2.2 Rev. D • ESD HBM (ESD STM 5.1) level ±1000V • Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level ±1000V The device meets ESD HBM (ESD STM 5.1) level ±1000V.
22.3 ATtiny9 22.3.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.3.2 Rev. D • ESD HBM (ESD STM 5.1) level ±1000V • Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level ±1000V The device meets ESD HBM (ESD STM 5.1) level ±1000V.
22.4 ATtiny10 22.4.1 Rev. E • Programming Lock Bits 1. Programming Lock Bits Programming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random. Problem Fix / Workaround When programming Lock Bits, make sure lock mode is not set to present, or lower levels. 22.4.2 Rev. C – D • ESD HBM (ESD STM 5.1) level ±1000V • Programming Lock Bits 1. ESD HBM (ESD STM 5.1) level ±1000V The device meets ESD HBM (ESD STM 5.
23. Datasheet Revision History 23.1 Rev. 8127F – 02/13 1. Updated: – Ordering information on page 152, page 153, page 154, and page 155 23.2 Rev. 8127E – 11/11 1. Updated: – Device status from Preliminary to Final – Ordering information on page 152, page 153, page 154, and page 155 23.3 Rev. 8127D – 02/10 1. Added UDFN package in “Features” on page 1, “Pin Configurations” on page 2, “Ordering Information” on page 152, and in “Packaging Information” on page 156 2.
– “SMCR – Sleep Mode Control Register” on page 25 – “PRR – Power Reduction Register” on page 26 – “Alternate Functions of Port B” on page 48 – “Overview” on page 82 – “Physical Layer of Tiny Programming Interface” on page 95 – “Overview” on page 106 – “ADC Characteristics (ATtiny5/10, only)” on page 119 – “Supply Current of I/O Modules” on page 121 – “Register Summary” on page 148 – “Ordering Information” on page 152 5.
ATtiny4/5/9/10 [DATASHEET] 8127F–AVR–02/2013 164
Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 Overview ................................................................................................... 3 2.1 3 4 5 6 7 Pin Description ..................................................................................................
7.4 8 9 Register Description ........................................................................................25 System Control and Reset ..................................................................... 27 8.1 Resetting the AVR ...........................................................................................27 8.2 Reset Sources .................................................................................................27 8.3 Watchdog Timer ................................
13.6 Changing Channel ...........................................................................................87 13.7 ADC Noise Canceler .......................................................................................87 13.8 Analog Input Circuitry ......................................................................................88 13.9 Noise Canceling Techniques ...........................................................................88 13.10 ADC Accuracy Definitions ...............
17.3 Idle Supply Current ........................................................................................125 17.4 Power-down Supply Current ..........................................................................127 17.5 Pin Pull-up .....................................................................................................128 17.6 Pin Driver Strength ........................................................................................131 17.7 Pin Threshold and Hysteresis ....
ATtiny4/5/9/10 [DATASHEET] 8127F–AVR–02/2013 5
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