Datasheet

941
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
2. These values are based on simulation. These values are not covered by test limits in production or
characterization.
3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of the ADC
clock.
Table 36-21. Differential Mode
Notes: 1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input
voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel com-
mon mode voltage):
a. If |VIN| > VREF/4
z VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
z VCM_IN > VREF/4 -0.05*VDDANA -0.1V
b. If |VIN| < VREF/4
z VCM_IN < 1.2*VDDANA - 0.75V
z VCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply. The ADC perfor-
mance of these pins will not be the same as all the other ADC channels on pins powered from the VDDANA power
supply.
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number Of Bits With gain compensation - 10.5 11.1 bits
TUE Total Unadjusted Error
I 1x Gain n
1.5 4.3 15.0 LSB
INL I Integral Non Linearity
1x Gain n
1.0 1.3 4.5 LSB
DNL Differential Non Linearity
1x Gain n
+/-0.3 +/-0.5 +/-0.95 LSB
I
I
I
Gain Error
Ext. Ref 1x -10.0 2.5 +10.0 mV
V
REF
=V
DDANA
/1.48 -15.0 -1.5 +10.0 mV
Bandgap -20.0 -5.0 +20.0 mV
Gain Accuracy
Ext. Ref. 0.5x +/-0.1 +/-0.2 +/-0.45 %
Ext. Ref. 2x to 16x +/-0.05 +/-0.1 +/-0.11 %
Offset Error
Ext. Ref. 1x -5.0 -1.5 +5.0 mV
V
REF
=V
DDANA
/1.48 -5.0 0.5 +5.0 mV
Bandgap -5.0 3.0 +5.0 mV
SFDR Spurious Free Dynamic Range
1x Gain
F
CLK_ADC
= 2.1MHz
F
IN
= 40kHz
A
IN
= 95%FSR
62.7 70.0 75.0 dB
SINAD Signal-to-Noise and Distortion 54.1 65.0 68.5 dB
SNR Signal-to-Noise Ratio 54.5 65.5 68.6 dB
THD Total Harmonic Distortion -77.0 -64.0 -63.0 dB
Noise RMS T=25°C 0.6 1.0 1.6 mV