Datasheet

836
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
32.6.3 Prescaler
The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates.
Refer to CTRLB for details on prescaler settings.
Figure 32-2. ADC Prescaler
The propagation delay of an ADC measurement is given by:
32.6.4 ADC Resolution
The ADC supports 8-bit, 10-bit and 12-bit resolutions. Resolution can be changed by writing the Resolution bit group in
the Control B register (CTRLB.RESSEL). After a reset, the resolution is set to 12 bits by default.
Table 32-1. Delay Gain
INTPUTCTRL.GAIN[3:0]
Delay Gain (in CLK_ADC Period)
Differential Mode Single-Ended Mode
0x0 0 0
0x1 0 1
0x2 1 1
0x3 1 2
0x4 2 2
0x5 ... 0xE Reserved Reserved
0xF 0 1
GCLK_ADC 9-BIT PRESCALER
CTRLB.PRESCALER[2:0]
DIV512
DIV256
DIV128
DIV64
DIV32
DIV16
DIV8
DIV4
CLK_ADC
PropagationDelay
1
Resolution
2
----------------------------
DelayGain++
f
CLK ADC–
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