Datasheet

350
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
The EEPROM bits indicates the Flash size reserved for EEPROM emulation according to the Table 21-3. EEPROM
resides in the upper rows of the NVM main address space and are writable, regardless of the region lock status.
Note: 1. the actual size of the EEPROM depends on the emulation software. For more information see Application Note AT03265
21.6.7 Security Bit
The security bit allows the entire chip to be locked from external access for code security. The security bit can be written
by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through a debugger
Chip Erase command. After issuing the SSB command, the PROGE error bit can be checked. Refer to “DSU – Device
Service Unit” on page 42 for details.
21.6.8 Cache
The NVM Controller cache reduces the device power consumption and improves system performance when wait states
are required. It is a direct-mapped cache that implements 8 lines of 64 bits (i.e., 64 bytes). NVM Controller cache can be
enabled by writing a zero in the CACHEDIS bit in the CTRLB register (CTRLB.CACHEDIS). Cache can be configured to
three different modes using the READMODE bit group in the CTRLB register. Refer to CTRLB register description for
more details. The INVALL command can be issued through the CTRLA register to invalidate all cache lines. Commands
affecting NVM content automatically invalidate cache lines.
3 16 4096
2 32 8192
1 64 16384
0 128 32768
Table 21-3. Flash size for EEPROM emulation
EEPROM[2:0] Rows Allocated to EEPROM EEPROM Size in Bytes for EEPROM emulation
(1)
7 None 0
6 1 256
5 2 512
4 4 1024
3 8 2048
2 16 4096
1 32 8192
0 64 16384
BOOTPROT [2:0] Rows Protected by BOOTPROT Boot Loader Size in Bytes