Datasheet

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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt
requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An
interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers
(SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt
enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority
field for each interrupt.
Peripheral Source NVIC Line
EIC NMI – External Interrupt Controller NMI
PM – Power Manager 0
SYSCTRL – System Control 1
WDT – Watchdog Timer 2
RTC – Real Time Counter 3
EIC – External Interrupt Controller 4
NVMCTRL – Non-Volatile Memory Controller 5
DMAC - Direct Memory Access Controller 6
USB - Universal Serial Bus 7
EVSYS – Event System 8
SERCOM0 – Serial Communication Interface 0 9
SERCOM1 – Serial Communication Interface 1 10
SERCOM2 – Serial Communication Interface 2 11
SERCOM3 – Serial Communication Interface 3 12
SERCOM4 – Serial Communication Interface 4 13
SERCOM5 – Serial Communication Interface 5 14
TCC0 – Timer Counter for Control 0 15
TCC1 – Timer Counter for Control 1 16
TCC2 – Timer Counter for Control 2 17
TC3 – Timer Counter 3 18
TC4 – Timer Counter 4 19
TC5 – Timer Counter 5 20
TC6 – Timer Counter 6 21
TC7 – Timer Counter 7 22
ADC – Analog-to-Digital Converter 23
AC – Analog Comparator 24
DAC – Digital-to-Analog Converter 25
PTC – Peripheral Touch Controller 26
I2S - Inter IC Sound 27