Datasheet

1008
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Register Summary and Register Description:
EVCTRL register: Added bits EXTINTO17 and EXTINTO16 in bit position 17 and 16 respectively.
INTENCLR, INTENSET, INTFLAG registers: Added bits EXTINT17 and EXTINT16 in bit position 17 and 16
respectively.
WAKEUP register: Added bits WAKEUPEN17 and WAKEUPEN16 in bit position 17 and 16 respectively.
CONFIG2 register added, CONFIG0 and CONFIG1 registers updated: Added bits FILTEN0...31 and SENSE0...31.
“NVMCTRL – Non-Volatile Memory Controller” on page 344
CTRLB register: Removed table from NVM Read Wait States description (RWS[3:0])
“PORT” on page 367
Instances of the term “pad” replaced with “pin”.
Instances of the term “bundle” replaced with “group” and “interface”.
“Basic Operation” on page 371 description updated.
Peripheral Multiplexing n (PMUX0) register: Offset formula updated.
“EVSYS – Event System” on page 394
Updated information in “Features” on page 394.
“Power Management” on page 395 updated: Description of on how event generators can generate an event when
the system clock is stopped moved to “Sleep Mode Operation” on page 400.
“Clocks” on page 395 updated: Renamed EVSYS channel dedicated generic clock from GCLK_EVSYS_x to
GCLK_EVSYS_CHANNELx.
Updated description in “Principle of Operation” on page 396.
Updated description in sub sections of “Basic Operation” on page 396.
Updated description in “The Overrun Channel x Interrupt” on page 400.
Channel x Overrun bit description in INTFLAG updated.
“SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter” on page 428
Updated description in “Break Character Detection and Auto-baud” on page 437.
Updated description in “Start-of-Frame Detection” on page 439.
“I2S - Inter-IC Sound Controller” on page 562
Introducing Frame Synch Clock.
“Signal Description” on page 563: Added separate tables for Master-, Slave- and Controller mode.
Updated description in “Debug Operation” on page 565 and “Register Access Protection” on page 565.
Updated description in “Principle of Operation” on page 566.
Updated description in sub sections of “Basic Operation” on page 568.
Updated formula in “MCKn Clock frequency” on page 569.
Updated formulas in “Relation between MCKn, SCKn and sampling frequency(fs)” on page 569.
Updated description in “PDM Reception” on page 573.
Section on MONO removed and information included in “Basic Operation” on page 568.
Updated property of Control A (CTRLA) register: Added Write-Synchronized
“TCC – Timer/Counter for Control Applications” on page 639