Datasheet

94
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
14.8.4 Generic Clock Generator Control
This register allows the user to configure one of the generic clock generators, as specified in the GENCTRL.ID bit group.
To write to the GENCTRL register, do a 32-bit write with all configurations and the ID.
To read the GENCTRL register, first do an 8-bit write to the GENCTRL.ID bit group with the ID of the generic clock
generator those configuration is to be read, and then read the GENCTRL register.
Name: GENCTRL
Offset: 0x4
Reset: 0x00010600
(1)
Property: Write-protected, Write-Synchronized
Note: 1. This is the reset value for Generator with ID =0. See Table 14-7 for reset value of other generators.
z Bits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 21 – RUNSTDBY: Run in Standby
This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated
GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if
a peripheral requires the clock.
0: The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero) will be dependent
on the setting in GENCTRL.OOV.
1: The generic clock generator is kept running and output to its dedicated GCLK_IO pin during standby mode.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
RUNSTDBY DIVSEL OE OOV IDC GENEN
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Bit151413121110 9 8
SRC[4:0]
Access R R R R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
ID[3:0]
Access R R R R R/W R/W R/W R/W
Reset00000000