Datasheet

85
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
14.6.4.2 Generic Clock Enable after Reset
The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a reset. That
means that the configuration of the generic clock generators and generic clocks after reset is device-dependent.
Refer to Table 14-7 and Table 14-8 for details on GENCTRL reset.
Refer to Table 14-11 and Table 14-12 for details on GENDIV reset.
Refer to Table 14-3 and Table 14-4 for details on CLKCTRL reset.
14.6.5 Sleep Mode Operation
14.6.5.1 SleepWalking
The GCLK module supports the SleepWalking feature. During a sleep mode where the generic clocks are stopped, a
peripheral that needs its generic clock to execute a process must request it from the Generic Clock Controller.
The Generic Clock Controller will receive this request and then determine which generic clock generator is involved and
which clock source needs to be awakened. It then wakes up the clock source, enables the generic clock generator and
generic clock stages successively and delivers the generic clock to the peripheral.
14.6.5.2 Run in Standby Mode
In standby mode, the GCLK can continuously output the generic clock generator output to GCLK_IO.
Refer to “Generic Clock Output on I/O Pins” on page 83 for details.
14.6.6 Synchronization
Due to the asynchronicity between CLK_GCLK_APB and GCLKGENSRC some registers must be synchronized when
accessed. A register can require:
z Synchronization when written
z Synchronization when read
z Synchronization when written and read
z No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following registers need synchronization when written:
z Generic Clock Generator Control register (GENCTRL)
z Generic Clock Generator Division register (GENDIV)
z Control register (CTRL)
Write-synchronization is denoted by the Write-Synchronization property in the register description.
Refer to “Register Synchronization” on page 74 for further details.