Datasheet

78
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in
the Generic Clock Generator. The total startup time from a clock request to the clock is available for the peripheral is:
Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock source periods
Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock source period
The delay for shutting down the clock source when there is no longer an active request is:
Delay_stop_min = 1 * divided clock source period + 1 * clock source period
Delay_stop_max = 2 * divided clock source periods + 2 * clock source periods
The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND bit located in
each clock source controller. The clock is always running whatever is the clock request. This has the effect to remove the
clock source startup time at the cost of the power consumption.
In standby mode, the clock request mechanism is still working if the modules are configured to run in standby mode
(RUNSTDBY bit).
13.6 Power Consumption vs Speed
Due to the nature of the asynchronous clocking of the peripherals there are some considerations that needs to be taken
if either targeting a low-power or a fast-acting system. If clocking a peripheral with a very low clock, the active power
consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock
domain is dependent on the peripheral clock speed, and will be longer with a slower peripheral clock; giving lower
response time and more time waiting for the synchronization to complete.
13.7 Clocks after Reset
On any reset the synchronous clocks start to their initial state:
z OSC8M is enabled and divided by 8
z GCLK_MAIN uses OSC8M as source
z CPU and BUS clocks are undivided
On a power reset the GCLK starts to their initial state:
z All generic clock generators disabled except:
z the generator 0 (GCLK_MAIN) using OSC8M as source, with no division
z the generator 2 using OSCULP32K as source, with no division
z All generic clocks disabled except:
z the WDT generic clock using the generator 2 as source
On a user reset the GCLK starts to their initial state, except for:
z generic clocks that are write-locked (WRTLOCK is written to one prior to reset or the WDT generic clock if the
WDT Always-On at power on bit set in the NVM User Row)
z The generic clock dedicated to the RTC if the RTC generic clock is enabled
On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are reset only by a
power reset.