Datasheet

77
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
13.3.7 Software Reset Write-Synchronization
Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set
STATUS.SYNCBUSY. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and
STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been reset. Writing a zero to the
CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset
write-synchronization.
When the software reset is in progress (STATUS.SYNCBUSY and CTRL.SWRST are one), attempt to do any of the
following will cause the peripheral bus to stall until the Software Reset synchronization and the reset is complete:
z Writing a core register
z Writing an APB register
z Reading a read-synchronized register
APB registers can be read while the software reset is being write-synchronized without causing the peripheral bus to
stall.
13.3.8 Synchronization Delay
The synchronization will delay the write or read access duration by a delay D, given by the equation:
Where is the period of the generic clock and is the period of the peripheral bus clock. A normal peripheral
bus register access duration is .
13.4 Enabling a Peripheral
To enable a peripheral clocked by a generic clock, the following parts of the system needs to be configured:
z A running clock source.
z A clock from the Generic Clock Generator must be configured to use one of the running clock sources, and the
generator must be enabled.
z The generic clock, through the Generic Clock Multiplexer, that connects to the peripheral needs to be configured
with a running clock from the Generic Clock Generator, and the generic clock must be enabled.
z The user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers will
read as all 0’s and any writes to the peripheral will be discarded.
13.5 On-demand, Clock Requests
Figure 13-4. Clock request routing
All the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state when
no peripherals are requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock
source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the
clock source is no longer needed and no peripheral have an active request the clock source will be stopped until
requested again. For the clock request to reach the clock source, the peripheral, the generic clock and the clock from the
Generic Clock Generator in-between must be enabled. The time taken from a clock request being asserted to the clock
5 P
GCLK
⋅ 2 P
APB
⋅+ D 6 P
GCLK
⋅ 3 P
APB
⋅+<<
P
GCLK
P
APB
2 P
APB
⋅
DFLL48M
G
eneric
C
lock
G
enerator
Clock request
G
eneric
C
lock
M
ulti
p
lexer
Clock request
P
er
iph
era
l
Clock request
ENABLE
RUNSTDBY
ONDEMAND
CLKEN
RUNSTDBY
ENABLE
RUNSTDBY
GENEN