Datasheet

598
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
32.12.3 SERCOM in I
2
C Mode Timing
Table 32-43 describes the requirements for devices connected to the I
2
C Interface Bus. Timing symbols refer to Figure
32-14.
Figure 32-14.I
2
C Interface Bus Timing
Table 32-43. I
2
C Interface Timing
(1)
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
2. Cb = Capacitive load on each bus line. Otherwise noted, value of C
b
set to 20pF.
3. These values are based on characterization. These values are not covered by test limits in production.
Symbol Parameter Conditions Min. Typ. Max. Units
t
R
Rise time for both SDA and SCL
(3)
I
- - 300
ns
t
OF
Output fall time from V
IHmin
to V
ILmax
(3)
10pF < C
b
(2)
< 400pF 7.0 10.0 50.0
t
HD;STA
Hold time (repeated) START condition f
SCL
> 100kHz, Master t
LOW
-9 - -
t
LOW
Low period of SCL Clock f
SCL
> 100kHz 113 - -
t
BUF
Bus free time between a STOP and a
START condition
f
SCL
> 100kHz t
LOW
- -
t
SU;STA
Setup time for a repeated START condition f
SCL
> 100kHz, Master t
LOW
+7 - -
t
HD;DAT
Data hold time f
SCL
> 100kHz, Master 9 - 12
t
SU;DAT
Data setup time f
SCL
> 100kHz, Master 104 - -
t
SU;STO
Setup time for STOP condition f
SCL
> 100kHz, Master t
LOW
+9 - -
t
SU;DAT;rx
Data setup time (receive mode) f
SCL
> 100kHz, Slave 51 - 56
t
HD;DAT;tx
Data hold time (send mode) f
SCL
> 100kHz, Slave 71 90 138
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
OF
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
t
R
SDA