Datasheet

543
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
30.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
30.5.1 I/O Lines
Using the DAC’s I/O lines requires the I/O pins to be configured using the port configuration (PORT).
Refer to “PORT” on page 280 for details.
30.5.2 Power Management
The DAC will continue to operate in any sleep mode where the selected source clock is running. The DAC interrupts can
be used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting
sleep modes. Refer to “PM – Power Manager” on page 101 for details on the different sleep modes.
30.5.3 Clocks
The DAC bus clock (CLK_DAC_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_DAC_APB can be found in the Peripheral Clock Masking section in “PM – Power Manager” on page 101.
A generic clock (GCLK_DAC) is required to clock the DAC. This clock must be configured and enabled in the Generic
Clock Controller before using the DAC. Refer to “GCLK – Generic Clock Controller” on page 79 for details.
This generic clock is asynchronous to the bus clock (CLK_DAC). Due to this asynchronicity, writes to certain registers will
require synchronization between the clock domains. Refer to “Synchronization” on page 546 for further details.
30.5.4 DMA
Not applicable.
30.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the DAC interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 25 for details.
30.5.6 Events
The events are connected to the Event System. Refer to “EVSYS – Event System” on page 306 for details on how to
configure the Event System.
30.5.7 Debug Operation
When the CPU is halted in debug mode the DAC continues normal operation. If the DAC is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging.
30.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following register:
z Interrupt Flag Status and Clear register (INTFLAG)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 28 for details.
30.5.9 Analog Connections
Not applicable.