Datasheet

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Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Table 29-9. Interrupt Selection
z Bit 4 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 3:2 – SPEED[1:0]: Speed Selection
This bit indicates the speed/propagation delay mode of comparator n. COMPCTRLn.SPEED can be written only
while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.
Table 29-10. Speed Selection
z Bit 1 – SINGLE: Single-Shot Mode
This bit determines the operation of comparator n. COMPCTRLn.SINGLE can be written only while COMPC-
TRLn.ENABLE is zero.
0: Comparator n operates in continuous measurement mode.
1: Comparator n operates in single-shot mode.
These bits are not synchronized.
z Bit 0 – ENABLE: Enable
Writing a zero to this bit disables comparator n.
Writing a one to this bit enables comparator n.
After writing to this bit, the value read back will not change until the action initiated by the writing is complete. Due
to synchronization, there is a latency of at least two GCLK_AC_DIG clock cycles from updating the register until
the comparator is enabled/disabled. The bit will continue to read the previous state while the change is in progress.
Writing a one to COMPCTRLn.ENABLE will prevent further changes to the other bits in COMPCTRLn. These bits
remain protected until COMPCTRLn.ENABLE is written to zero and the write is synchronized.
Value Name Description
0x0 TOGGLE Interrupt on comparator output toggle
0x1 RISING Interrupt on comparator output rising
0x2 FALLING Interrupt on comparator output falling
0x3 EOC Interrupt on end of comparison (single-shot mode only)
Value Name Description
0x0 LOW Low speed
0x1 HIGH High speed
0x2-0x3 Reserved