Datasheet

539
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Table 29-5. Filter Length
z Bits 23:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 19 – HYST: Hysteresis Enable
This bit indicates the hysteresis mode of comparator n. Hysteresis is available only for continuous mode (COMPC-
TRLn.SINGLE=0). COMPCTRLn.HYST can be written only while COMPCTRLn.ENABLE is zero.
0: Hysteresis is disabled.
1: Hysteresis is enabled.
These bits are not synchronized.
z Bit 18 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 17:16 – OUT[1:0]: Output
These bits configure the output selection for comparator n. COMPCTRLn.OUT can be written only while COMPC-
TRLn.ENABLE is zero.
These bits are not synchronized.
Table 29-6. Output Selection
z Bit 15 – SWAP: Swap Inputs and Invert
This bit swaps the positive and negative inputs to COMPn and inverts the output. This function can be used for off-
set cancellation. COMPCTRLn.SWAP can be written only while COMPCTRLn.ENABLE is zero.
0: The output of MUXPOS connects to the positive input, and the output of MUXNEG connects to the negative
input.
1: The output of MUXNEG connects to the positive input, and the output of MUXPOS connects to the negative
input.
These bits are not synchronized.
Value Name Description
0x0 OFF No filtering
0x1 MAJ3 3-bit majority function (2 of 3)
0x2 MAJ5 5-bit majority function (3 of 5)
0x3-0x7 N/A Reserved
Value Name Description
0x0 OFF
The output of COMPn is not routed to the COMPn I/O
port
0x1 ASYNC
The asynchronous output of COMPn is routed to the
COMPn I/O port
0x2 SYNC
The synchronous output (including filtering) of COMPn
is routed to the COMPn I/O port
0x3 N/A Reserved