Datasheet

493
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
28.8.5 Control B
Name: CTRLB
Offset: 0x04
Reset: 0x0000
Property: Write-Synchronized, Write-Protected
z Bits 15:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 10:8 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock according to Table 28-7. These bits can only be
written while the ADC is disabled.
Table 28-7. Prescaler Configuration
z Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 5:4 – RESSEL[1:0]: Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution. These bits can
be written only while the ADC is disabled.
Bit 151413121110 9 8
PRESCALER[2:0]
AccessRRRRRR/WR/WR/W
Reset00000000
Bit76543210
RESSEL[1:0] CORREN FREERUN LEFTADJ DIFFMODE
Access R R R/W R/W R/W R/W R/W R/W
Reset00000000
Value Name Description
0x0 DIV4 Peripheral clock divided by 4
0x1 DIV8 Peripheral clock divided by 8
0x2 DIV16 Peripheral clock divided by 16
0x3 DIV32 Peripheral clock divided by 32
0x4 DIV64 Peripheral clock divided by 64
0x5 DIV128 Peripheral clock divided by 128
0x6 DIV256 Peripheral clock divided by 256
0x7 DIV512 Peripheral clock divided by 512