Datasheet

484
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag
is cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. This is device dependent.
Refer to “Nested Vector Interrupt Controller” on page 25 for details. If the peripheral has one common interrupt request
line for all the interrupt sources, the user must read the INTFLAG register to determine which interrupt condition is
present.
28.6.12 Events
The peripheral can generate the following output events:
z Result Ready (RESRDY)
z Window Monitor (WINMON)
Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register
(EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output
event. The events must be correctly routed in the Event System. Refer to “EVSYS – Event System” on page 306 for
details.
The peripheral can take the following actions on an input event:
z ADC start conversion (START)
z ADC conversion flush (FLUSH)
Input events must be enabled for the corresponding action to be taken on any input event. Writing a one to an Event
Input bit in the Event Control register (EVCTRL.xxEI) enables the corresponding action on the input event. Writing a zero
to this bit disables the corresponding action on the input event. Note that if several events are connected to the
peripheral, the enabled action will be taken on any of the incoming events. The events must be correctly routed in the
Event System. Refer to “EVSYS – Event System” on page 306 for details.
28.6.13 Sleep Mode Operation
The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the ADC during standby
sleep mode. When the bit is zero, the ADC is disabled during sleep, but maintains its current configuration. When
the bit is one, the ADC continues to operate during sleep. Note that when RUNSTDBY is zero, the analog
blocks are powered off for the lowest power consumption. This necessitates a start-up time delay when the system
returns from sleep.
When RUNSTDBY is one, any enabled ADC interrupt source can wake up the CPU. While the CPU is sleeping, ADC
conversion can only be triggered by events.
28.6.14 Synchronization
Due to the asynchronicity between CLK_ADC_APB and GCLK_ADC, some registers must be synchronized when
accessed. A register can require:
z Synchronization when written
z Synchronization when read
z Synchronization when written and read
z No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete.