Datasheet

45
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
read. The DCC0 and DCC1 registers are shared with the onboard memory testing logic (MBIST). Accordingly, DCC0 and
DCC1 must not be used while performing MBIST operations.
12.11.5 Testing of Onboard Memories (MBIST)
The DSU implements a feature for automatic testing of memory also known as MBIST. This is primarily intended for
production test of onboard memories. MBIST cannot be operated from the external address range when the device is
protected by the NVMCTRL security bit (refer to “Security Bit” on page 264). If a MBIST command is issued when the
device is protected, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR).
1. Algorithm
The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a
wide range of memory defects, while still keeping a linear run time. The algorithm is:
1. Write entire memory to 0, in any order.
2. Bit for bit read 0, write 1, in descending order.
3. Bit for bit read 1, write 0, read 0, write 1, in ascending order.
4. Bit for bit read 1, write 0, in ascending order.
5. Bit for bit read 0, write 1, read 1, write 0, in ascending order.
6. Read 0 from entire memory, in ascending order.
The specific implementation used has a run time of O(14n) where n is the number of bits in the RAM. The detected
faults are:
z Address decoder faults
z Stuck-at faults
z Transition faults
z Coupling faults
z Linked Coupling faults
z Stuck-open faults
2. Starting MBIST
To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit group, and the size of
the memory into the Length register. See “Physical Memory Map” on page 20 to know which memories are avail-
able, and which address they are at.
For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a sub-
set of a memory, but the test coverage will then be somewhat lower.
The actual test is started by writing a one to CTRL.MBIST. A running MBIST operation can be canceled by writing
a one to CTRL.SWRST.
3. Interpreting the Results
The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set.
There are three different modes:
z ADDR.AMOD=0: exit-on-error (default)
In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both cases,
STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read the DATA and
ADDR registers to locate the fault. Refer to “Locating Errors” on page 45.
z ADDR.AMOD=1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only STATUSA.FAIL is
asserted. The state machine waits for user to clear STATUSA.FAIL by writing a one in STATUSA.FAIL to resume.
Prior to resuming, user can read the DATA and ADDR registers to locate the fault. Refer to “Locating Errors” on
page 45.
4. Locating Errors
If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error.
The position of the failing bit can be found by reading the following registers: