Datasheet

440
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
When a retrigger is evoked with the counter stopped, the counter will continue counting from the value in the COUNT
register.
Note: When retrigger event action is configured and enabled as an event action, enabling the counter will not start the
counter. The counter will start at the next incoming event and restart on any following event.
Count Event Action
When the count event action is configured, every new incoming event will make the counter increment or decrement,
depending on the state of the direction bit (CTRLBSET.DIR).
Start Event Action
When the TC is configured with a start event action in the EVCTRL.EVACT bit group, enabling the TC does not make the
counter start; the start is postponed until the next input event or software retrigger action. When the counter is running,
an input event has not effect on the counter.
27.6.2.6 Compare Operations
When using the TC with the Compare/Capture Value registers (CCx) configured for compare operation, the counter
value is continuously compared to the values in the CCx registers. This can be used for timer or waveform operation.
Waveform Output Operations
The compare channels can be used for waveform generation on the corresponding I/O pins. To make the waveform
visible on the connected pin, the following requirements must be fulfilled:
z Choose a waveform generation operation
z Optionally, invert the waveform output by writing the corresponding Waveform Output Invert Enable bit in the
Control C register (CTRLC.INVx)
z Enable the corresponding multiplexor in the PORT
The counter value is continuously compared with each CCx available. When a compare match occurs, the Match or
Capture Channel x interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.MCx) is set on the next zero-to-
one transition of CLK_TC_CNT (see Figure 27-4). An interrupt and/or event can be generated on such a condition when
INTENSET.MCx and/or EVCTRL.MCEOx is one.
One of four configurations in the Waveform Generation Operation bit group in the Control A register (CTRLA.WAVEGEN)
must be chosen to perform waveform generation. This will influence how the waveform is generated and impose
restrictions on the top value. The four configurations are:
z Normal frequency (NFRQ)
z Match frequency (MFRQ)
z Normal PWM (NPWM)
z Match PWM (MPWM)
When using NPWM or NFRQ, the top value is determined by the counter mode. In 8-bit mode, the Period register (PER)
is used as the top value and the top value can be changed by writing to the PER register. In 16- and 32-bit mode, the top
value is fixed to the maximum value of the counter.
Frequency Operation
When NFRQ is used, the waveform output (WO[x]) toggles every time CCx and the counter are equal, and the interrupt
flag corresponding to that channel will be set.