Datasheet

436
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
27.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
27.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
27.5.1 I/O Lines
Using the TC’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 280 for details.
27.5.2 Power Management
The TC can continue to operate in any sleep mode where the selected source clock is running. The TC interrupts can be
used to wake up the device from sleep modes. The events can trigger other operations in the system without exiting
sleep modes. Refer to “PM – Power Manager” on page 101 for details on the different sleep modes.
27.5.3 Clocks
The TC bus clock (CLK_TCx_APB, where x represents the specific TC instance number) can be enabled and disabled in
the Power Manager, and the default state of CLK_TCx_APB can be found in the Peripheral Clock Masking section in
“PM – Power Manager” on page 101.
The different TC instances are paired, even and odd, starting from TC0, and use the same generic clock, GCLK_TCx.
This means that the TC instances in a TC pair cannot be set up to use different GCLK_TCx clocks.
This generic clock is asynchronous to the user interface clock (CLK_TCx_APB). Due to this asynchronicity, accessing
certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page 445 for
further details.
27.5.4 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the TC interrupts requires the interrupt controller
to be configured first. Refer to “Nested Vector Interrupt Controller” on page 25 for details.
27.5.5 Events
To use the TC event functionality, the corresponding events need to be configured in the event system. Refer to “EVSYS
– Event System” on page 306 for details.
27.5.6 Debug Operation
When the CPU is halted in debug mode the TC will halt normal operation. The TC can be forced to continue operation
during debugging. Refer to the DBGCTRL register for details.
27.5.7 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
z Interrupt Flag register (INTFLAG)
z Status register (STATUS)
Signal Name Type Description
WO[1:0] Digital output Waveform output