Datasheet

431
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Table 26-9. Bus State
When the master is disabled, the bus-state is unknown. When in the unknown state, writing 0x1 to BUSSTATE forces the
bus state into the idle state. The bus state cannot be forced into any other state.
Writing STATUS.BUSSTATE to idle will set STATUS.SYNCBUSY.
z Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bit 2 – RXNACK: Received Not Acknowledge
This bit indicates whether the last address or data packet sent was acknowledged or not.
0: Slave responded with ACK.
1: Slave responded with NACK.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is not write-synchronized.
z Bit 1 – ARBLOST: Arbitration Lost
The Arbitration Lost flag (STATUS.ARBLOST) is set if arbitration is lost while transmitting a high data bit or a
NACK bit, or while issuing a start or repeated start condition on the bus. The Master on Bus interrupt flag (INT-
FLAG.MB) will be set when STATUS.ARBLOST is set.
Writing the ADDR.ADDR register will automatically clear STATUS.ARBLOST.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
This bit is not write-synchronized.
z Bit 0 – BUSERR: Bus Error
The Bus Error bit (STATUS.BUSERR) indicates that an illegal bus condition has occurred on the bus, regardless
of bus ownership. An illegal bus condition is detected if a protocol violating start, repeated start or stop is detected
on the I
2
C bus lines. A start condition directly followed by a stop condition is one example of a protocol violation. If
a time-out occurs during a frame, this is also considered a protocol violation, and will set BUSERR.
If the I
2
C master is the bus owner at the time a bus error occurs, STATUS.ARBLOST and INTFLAG.MB will be set
in addition to BUSERR.
Writing the ADDR.ADDR register will automatically clear the BUSERR flag.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear it.
This bit is not write-synchronized.
Value Name Description
0x0 Unknown
The bus state is unknown to the I
2
C master and will wait for a stop condition to be
detected or wait to be forced into an idle state by software
0x1 Idle The bus state is waiting for a transaction to be initialized
0x2 Owner The I
2
C master is the current owner of the bus
0x3 Busy Some other I
2
C master owns the bus