Datasheet

430
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
26.8.2.8 Status
Name: STATUS
Offset: 0x10
Reset: 0x0000
Property: Write-Synchronized
z Bit 15 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
z Bits 14:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 7 – CLKHOLD: Clock Hold
The Master Clock Hold flag (STATUS.CLKHOLD) is set when the master is holding the SCL line low, stretching
the I
2
C clock. Software should consider this bit a read-only status flag that is set when INTFLAG.SB or INT-
FLAG.MB is set. When the corresponding interrupt flag is cleared and the next operation is given, this bit is
automatically cleared.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is not write-synchronized.
z Bit 6 – LOWTOUT: SCL Low Time-Out
This bit is set if an SCL low time-out occurs.
Writing a one to this bit location will clear STATUS.LOWTOUT. Normal use of the I
2
C interface does not require
the LOWTOUT flag to be cleared by this method. This flag is automatically cleared when writing to the ADDR
register.
Writing a zero to this bit has no effect.
This bit is not write-synchronized.
z Bits 5:4 – BUSSTATE[1:0]: Bus State
These bits indicate the current I
2
C bus state as defined in Table 26-9. After enabling the SERCOM as an I
2
C mas-
ter, the bus state will be unknown.
Bit151413121110 9 8
SYNCBUSY
AccessRRRRRRRR
Reset00000000
Bit76543210
CLKHOLD LOWTOUT BUSSTATE[1:0] RXNACK ARBLOST BUSERR
Access R R/W R R/W R R R/W R/W
Reset00000000