Datasheet

421
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Enabling this option is necessary for SMBus compatibility, but can also be used in a non-SMBus set-up.
Table 26-6. Inactive Timout
Calculated time-out periods are based on a 100kHz baud rate.
These bits are not synchronized.
z Bits 27:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 21:20 – SDAHOLD[1:0]: SDA Hold Time
These bits define the SDA hold time with respect to the negative edge of SCL.
Table 26-7. SDA Hold Time
These bits are not synchronized.
z Bits 19:17 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 16 – PINOUT: Pin Usage
This bit set the pin usage to either two- or four-wire operation:
0: 4-wire operation disabled.
1: 4-wire operation enabled.
This bit is not synchronized.
z Bits 15:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 7 – RUNSTDBY: Run in Standby
This bit defines the functionality in standby sleep mode.
0: GCLK_SERCOMx_CORE is disabled and the I
2
C master will not operate in standby sleep mode.
1: GCLK_SERCOMx_CORE is enabled in all sleep modes allowing the master to operate in standby sleep mode.
This bit is not synchronized.
Value Name Description
0x0 DIS Disabled
0x1 55US 5-6 SCL cycle time-out (50-60µs)
0x2 105US 10-11 SCL cycle time-out (100-110µs)
0x3 205US 20-21 SCL cycle time-out (200-210µs)
Value Name Description
0x0 DIS Disabled
0x1 75NS 50-100ns hold time
0x2 450NS 300-600ns hold time
0x3 600NS 400-800ns hold time