Datasheet

41
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
tem continues to be held in this static state until the internally regulated supplies have reached a safe operating
state.
2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks
that do not have clock gate control). Internal resets are maintained due to the external reset.
3. The debugger maintains a low level on SWCLK. Releasing RESET
results in a debugger Cold-Plugging
procedure.
4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
5. The CPU remains in reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released.
6. A Chip-Erase is issued to ensure that the flash is fully erased prior to programming.
7. Programming is available through the AHB-AP.
8. After operation is completed, the chip can be restarted either by asserting RESET
, toggling power or writing a one
to the Status A register CPU Reset Phase Extension bit (STATUSA.CRSTEXT). Make sure that the SWCLK pin is
high when releasing RESET
to prevent extending the CPU reset.
12.9 Intellectual Property Protection
Intellectual property protection consists of restricting access to internal memories from external tools when the device is
protected, and is accomplished by setting the NVMCTRL security bit (refer to “Security Bit” on page 264). This protected
state can be removed by issuing a Chip-Erase (refer to “Chip-Erase” on page 40). When the device is protected,
read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted.
The DSU implements a security filter that monitors the AHB transactions generated by the ARM AHB-AP inside the DAP.
If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded,
causing an error response that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture
Specification on http://www.arm.com).
The DSU is intended to be accessed either:
z Internally from the CPU, without any limitation, even when the device is protected
z Externally from a debug adapter, with some restrictions when the device is protected
For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses
from internal ones, the first 0x100 bytes of the DSU register map have been replicated at offset 0x100:
z The first 0x100 bytes form the internal address range
z The next 0x100 bytes form the external address range
When the device is protected, the DAP can only issue MEM-AP accesses in the DSU address range limited to the 0x100-
0x2000 offset range.
The DSU operating registers are located in the 0x00-0xFF area and remapped in 0x100-0x1FF to differentiate accesses
coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x100-0x1FF, it is
subject to security restrictions. For more information, refer to Table 12-1.