Datasheet

396
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
The missing ACK response can indicate that the I
2
C slave is busy with other tasks or sleeping and, therefore, not able to
respond. In this event, the next step can be either issuing a stop condition (recommended) or resending the address
packet by using a repeated start condition. However, the reason for the missing acknowledge can be that an invalid I
2
C
slave address has been used or that the I
2
C slave is for some reason disconnected or faulty. If using SMBus logic, the
slave must ACK the address, and hence no action means the slave is not available on the bus.
Case 3: Address packet transmit complete – Write packet, Master on Bus set
If the I
2
C master receives an acknowledge response from the I
2
C slave, INTFLAG.MB is set and STATUS.RXNACK is
cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I
2
C
operation to continue. The three options are:
z The data transmit operation is initiated by writing the data byte to be transmitted into DATA.DATA.
z Transmit a new address packet by writing ADDR.ADDR. A repeated start condition will automatically be
inserted before the address packet.
z Issue a stop condition, consequently terminating the transaction.
Case 4: Address packet transmit complete – Read packet, Slave on Bus set
If the I
2
C master receives an ACK from the I
2
C slave, the I
2
C master proceeds to receive the next byte of data from the
I
2
C slave. When the first data byte is received, the Slave on Bus bit in the Interrupt Flag register (INTFLAG.SB) is set and
STATUS.RXNACK is cleared. The clock hold is active at this point, preventing further activity on the bus.
In this case, the software implementation becomes highly protocol dependent. Three possible actions can enable the I
2
C
operation to continue. The three options are:
z Let the I
2
C master continue to read data by first acknowledging the data received. This is automatically done
when reading DATA.DATA if the smart mode is enabled.
z Transmit a new address packet.
z Terminate the transaction by issuing a stop condition.
An ACK or NACK will be automatically transmitted for the last two alternatives if smart mode is enabled. The
Acknowledge Action bit in the Control B register (CTRLB.ACKACT) determines whether ACK or NACK should be sent.
Transmitting Data Packets
When an address packet with direction set to write (STATUS.DIR is zero) has been successfully transmitted,
INTFLAG.MB will be set and the I
2
C master can start transmitting data by writing to DATA.DATA. The I
2
C master
transmits data via the I
2
C bus while continuously monitoring for packet collisions. If a collision is detected, the I
2
C master
looses arbitration and STATUS.ARBLOST is set. If the transmit was successful, the I
2
C master automatically receives an
ACK bit from the I
2
C slave and STATUS.RXNACK will be cleared. INTFLAG.MB will be set in both cases, regardless of
arbitration outcome.
Testing STATUS.ARBLOST and handling the arbitration lost condition in the beginning of the I
2
C Master on Bus interrupt
is recommended. This can be done, as there is no difference between handling address and data packet arbitration.
STATUS.RXNACK must be checked for each data packet transmitted before the next data packet transmission can
commence. The I
2
C master is not allowed to continue transmitting data packets if a NACK is given from the I
2
C slave.
Receiving Data Packets
When INTFLAG.SB is set, the I
2
C master will already have received one data packet. The I
2
C master must respond by
sending either an ACK or NACK. Sending a NACK might not be successfully executed as arbitration can be lost during
the transmission. In this case, a loss of arbitration will cause INTFLAG.SB to not be set on completion. Instead,
INTFLAG.MB will be used to indicate a change in arbitration. Handling of lost arbitration is the same as for data bit
transmission.
26.6.2.6 I
2
C Slave Operation
The I
2
C slave is byte-oriented and interrupt-based. The number of interrupts generated is kept at a minimum by
automatic handling of most events. Auto triggering of operations and a special smart mode, which can be enabled by