Datasheet

392
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Figure 26-4. Bus State Diagram
The bus state machine is active when the I
2
C master is enabled. After the I
2
C master has been enabled, the bus state is
unknown. From the unknown state, the bus state machine can be forced to enter the idle state by writing to
STATUS.BUSSTATE accordingly. However, if no action is taken by software, the bus state will become idle if a stop
condition is detected on the bus. If the inactive bus time-out is enabled, the bus state will change from unknown to idle on
the occurrence of a time-out. Note that after a known bus state is established, the bus state logic will not re-enter the
unknown state from either of the other states.
When the bus is idle it is ready for a new transaction. If a start condition is issued on the bus by another I
2
C master in a
multimaster setup, the bus becomes busy until a stop condition is detected. The stop condition will cause the bus to re-
enter the IDLE state. If the inactive bus time-out (SMBus) is enabled, the bus state will change from busy to idle on the
occurrence of a time-out. If a start condition is generated internally by writing the Address bit group in the Address
register (ADDR.ADDR) while in idle state, the owner state is entered. If the complete transaction was performed without
interference, i.e., arbitration not lost, the I
2
C master is allowed to issue a stop condition, which in turn will cause a change
of the bus state back to idle. However, if a packet collision is detected when in the owner state, the arbitration is assumed
lost and the bus state becomes busy until a stop condition is detected.
A repeated start condition will change the bus state only if arbitration is lost while issuing a repeated start.
26.6.2.4 Clock Generation
The Master I
2
C clock (SCL) frequency is determined by a number of factors. The low (T
LOW
) and high (T
_HIGH
) times are
determined by the Baud Rate register (BAUD), while the rise (T
RISE
) and fall (T
FALL
) times are determined by the bus
topology. Because of the wired-AND logic of the bus, T
FALL
will be considered as part of T
LOW
. Likewise, T
RISE
will be in a
state between T
LOW
and T
HIGH
until a high state has been detected.
P + Timeout
RESET
Wri te ADDR
(S)
IDLE
(0b01)
S
BUSY
(0b11)
P + Ti meout
UNKNOWN
(0b00)
OWNER
(0b10)
Arbitration
Lost
Command P
Wri te ADDR (Sr )
Sr