Datasheet

391
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Any writes to these bits or registers when the I
2
C interface is enabled or is being enabled (CTRLA.ENABLE is one) will
be discarded. Writes to these registers while the I
2
C interface is being disabled will be completed after the disabling is
complete.
Enable-protection is denoted by the Enable-Protection property in the register description.
Before the I
2
C interface is enabled, it must be configured as outlined by the following steps:
I
2
C mode in master or slave operation must be selected by writing 0x4 or 0x5 to the Operating Mode bit group in the
Control A register (CTRLA.MODE)
z SCL low time-out can be enabled by writing to the SCL Low Time-Out bit in the Control A register
(CTRLA.LOWTOUT)
z In master operation, the inactive bus time-out can be set in the Inactive Time-Out bit group in the Control A
register (CTRLA.INACTOUT)
z Hold time for SDA can be set in the SDA Hold Time bit group in the Control A register (CTRLA.SDAHOLD)
z Smart operation can be enabled by writing to the Smart Mode Enable bit in the Control B register
(CTRLB.SMEN)
z In slave operation, the address match configuration must be set in the Address Mode bit group in the
Control B register (CTRLB.AMODE)
z In slave operation, the addresses must be set, according to the selected address configuration, in the
Address and Address Mask bit groups in the Address register (ADDR.ADDR and ADDR.ADDRMASK)
z In master operation, the Baud Rate register (BAUD) must be written to generate the desired baud rate
26.6.2.2 Enabling, Disabling and Resetting
The I
2
C interface is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The I
2
C
interface is disabled by writing a zero to CTRLA.ENABLE. The I
2
C interface is reset by writing a one to the Software
Reset bit in the Control A register (CTRLA.SWRST). All registers in the I
2
C interface, except DBGCTRL, will be reset to
their initial state, and the I
2
C interface will be disabled. Refer to CTRLA for details.
26.6.2.3 I
2
C Bus State Logic
The bus state logic includes several logic blocks that continuously monitor the activity on the I
2
C bus lines in all sleep
modes. The start and stop detectors and the bit counter are all essential in the process of determining the current bus
state. The bus state is determined according to the state diagram shown in Figure 26-4. Software can get the current bus
state by reading the Master Bus State bits in the Status register (STATUS.BUSSTATE). The value of
STATUS.BUSSTATE in the figure is shown in binary.