Datasheet

389
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
26.5.7 Debug Operation
When the CPU is halted in debug mode, the I
2
C interface continues normal operation. If the I
2
C interface is configured in
a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging. The I
2
C interface can be forced to halt operation during debugging.
Refer to the DBGCTRL register for details.
26.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
z Interrupt Flag Status and Clear register (INTFLAG
z Status register (STATUS)
z Address register (ADDR)
z Data register (DATA)
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through en external debugger. Refer to “PAC – Peripheral Access
Controller” on page 28 for details.
26.5.9 Analog Connections
Not applicable.
26.6 Functional Description
26.6.1 Principle of Operation
The I
2
C interface uses two physical lines for communication:
z Serial Data Line (SDA) for packet transfer
z Serial Clock Line (SCL) for the bus clock
A transaction starts with the start condition, followed by a 7-bit address and a direction bit (read or write) sent from the I
2
C
master. The addressed I
2
C slave will then acknowledge (ACK) the address, and data packet transactions can
commence. Every 9-bit data packet consists of 8 data bits followed by a one-bit reply indicating whether the data was
acknowledged or not. In the event that a data packet is not acknowledged (NACK), whether sent from the I
2
C slave or
master, it will be up to the I
2
C master to either terminate the connection by issuing the stop condition, or send a repeated
start if more data is to be transceived.
Figure 26-2 illustrates the possible transaction formats and Figure 26-3 explains the legend used.