Datasheet

388
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
26.4 Signal Description
Refer to “I/O Multiplexing and Considerations” on page 11 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins. Note that not all the pins are I
2
C pins. Refer to Table 5-1 for details on the pin type for
each pin.
26.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
26.5.1 I/O Lines
Using the SERCOM’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 280 for details.
26.5.2 Power Management
The I
2
C will continue to operate in any sleep mode where the selected source clock is running. I
2
C interrupts can be used
to wake up the device from sleep modes. The events can trigger other operations in the system without exiting sleep
modes. Refer to “PM – Power Manager” on page 101 for details on the different sleep modes.
26.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB, where i represents the specific SERCOM instance number) is enabled
by default, and can be enabled and disabled in the Power Manager. Refer to “PM – Power Manager” on page 101 for
details.
The SERCOM bus clock (CLK_SERCOMx_APB) is enabled by default, and can be enabled and disabled in the Power
Manager. Refer to “PM – Power Manager” on page 101 for details.
Two generic clocks are used by the SERCOM (GCLK_SERCOMx_CORE and GCLK_SERCOM_SLOW). The core clock
(GCLK_SERCOMx_CORE) is required to clock the SERCOM while operating as a master, while the slow clock
(GCLK_SERCOM_SLOW) is required only for certain functions. These clocks must be configured and enabled in the
Generic Clock Controller (GCLK) before using the SERCOM. Refer to “GCLK – Generic Clock Controller” on page 79 for
details.
These generic clocks are asynchronous to the SERCOM bus clock (CLK_SERCOMx_APB). Due to this asynchronicity,
writes to certain registers will require synchronization between the clock domains. Refer to the “Synchronization” on page
400 section for further details.
26.5.4 DMA
Not applicable.
26.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the I
2
C interrupts requires the Interrupt Controller
to be configured first. Refer to “Nested Vector Interrupt Controller” on page 25 for details.
26.5.6 Events
Not applicable.
Signal Name Type Description
PAD[0] Digital I/O SDA
PAD[1] Digital I/O SCL
PAD[2] Digital I/O SDA_OUT (4-wire)
PAD[3] Digital I/O SDC_OUT (4-wire)