Datasheet
Table Of Contents
- Description
- Features
- 1. Configuration Summary
- 2. Ordering Information
- 3. Block Diagram
- 4. Pinout
- 5. I/O Multiplexing and Considerations
- 6. Signal Descriptions List
- 7. Power Supply and Start-Up Considerations
- 8. Product Mapping
- 9. Memories
- 10. Processor and Architecture
- 11. Peripherals Configuration Overview
- 12. DSU – Device Service Unit
- 12.1 Overview
- 12.2 Features
- 12.3 Block Diagram
- 12.4 Signal Description
- 12.5 Product Dependencies
- 12.6 Debug Operation
- 12.7 Chip-Erase
- 12.8 Programming
- 12.9 Intellectual Property Protection
- 12.10 Device Identification
- 12.11 Functional Description
- 12.12 Register Summary
- 12.13 Register Description
- 12.13.1 Control
- 12.13.2 Status A
- 12.13.3 Status B
- 12.13.4 Address
- 12.13.5 Length
- 12.13.6 Data
- 12.13.7 Debug Communication Channel n
- 12.13.8 Device Identification
- 12.13.9 CoreSight ROM Table Entry n
- 12.13.10 CoreSight ROM Table End
- 12.13.11 Coresight ROM Table Memory Type
- 12.13.12 Peripheral Identification 4
- 12.13.13 Peripheral Identification 0
- 12.13.14 Peripheral Identification 1
- 12.13.15 Peripheral Identification 2
- 12.13.16 Peripheral Identification 3
- 12.13.17 Component Identification 0
- 12.13.18 Component Identification 1
- 12.13.19 Component Identification 2
- 12.13.20 Component Identification 3
- 13. Clock System
- 14. GCLK – Generic Clock Controller
- 14.1 Overview
- 14.2 Features
- 14.3 Block Diagram
- 14.4 Signal Description
- 14.5 Product Dependencies
- 14.6 Functional Description
- 14.6.1 Principle of Operation
- 14.6.2 Basic Operation
- 14.6.2.1 Initialization
- 14.6.2.2 Enabling, Disabling and Resetting
- 14.6.2.3 Generic Clock Generator
- 14.6.2.4 Enabling a Generic Clock Generator
- 14.6.2.5 Disabling a Generic Clock Generator
- 14.6.2.6 Selecting a Clock Source for the Generic Clock Generator
- 14.6.2.7 Changing Clock Frequency
- 14.6.2.8 Duty Cycle
- 14.6.2.9 Generic Clock Output on I/O Pins
- 14.6.3 Generic Clock
- 14.6.4 Additional Features
- 14.6.5 Sleep Mode Operation
- 14.6.6 Synchronization
- 14.7 Register Summary
- 14.8 Register Description
- 15. PM – Power Manager
- 15.1 Overview
- 15.2 Features
- 15.3 Block Diagram
- 15.4 Signal Description
- 15.5 Product Dependencies
- 15.6 Functional Description
- 15.6.1 Principle of Operation
- 15.6.2 Basic Operation
- 15.6.2.1 Initialization
- 15.6.2.2 Enabling, Disabling and Resetting
- 15.6.2.3 Selecting the Main Clock Source
- 15.6.2.4 Selecting the Synchronous Clock Division Ratio
- 15.6.2.5 Clock Ready Flag
- 15.6.2.6 Peripheral Clock Masking
- 15.6.2.7 Clock Failure Detector
- 15.6.2.8 Reset Controller
- 15.6.2.9 Sleep Mode Controller
- 15.6.3 SleepWalking
- 15.6.4 Interrupts
- 15.6.5 Events
- 15.6.6 Sleep Mode Operation
- 15.7 Register Summary
- 15.8 Register Description
- 15.8.1 Control
- 15.8.2 Sleep Mode
- 15.8.3 CPU Clock Select
- 15.8.4 APBA Clock Select
- 15.8.5 APBB Clock Select
- 15.8.6 APBC Clock Select
- 15.8.7 AHB Mask
- 15.8.8 APBA Mask
- 15.8.9 APBB Mask
- 15.8.10 APBC Mask
- 15.8.11 Interrupt Enable Clear
- 15.8.12 Interrupt Enable Set
- 15.8.13 Interrupt Flag Status and Clear
- 15.8.14 Reset Cause
- 16. SYSCTRL – System Controller
- 16.1 Overview
- 16.2 Features
- 16.3 Block Diagram
- 16.4 Signal Description
- 16.5 Product Dependencies
- 16.6 Functional Description
- 16.6.1 Principle of Operation
- 16.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation
- 16.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation
- 16.6.4 32kHz Internal Oscillator (OSC32K) Operation
- 16.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
- 16.6.6 8MHz Internal Oscillator (OSC8M) Operation
- 16.6.7 Digital Frequency Locked Loop (DFLL48M) Operation
- 16.6.8 3.3V Brown-Out Detector Operation
- 16.6.9 Voltage Reference System Operation
- 16.6.10 Interrupts
- 16.6.11 Synchronization
- 16.7 Register Summary
- 16.8 Register Description
- 16.8.1 Interrupt Enable Clear
- 16.8.2 Interrupt Enable Set
- 16.8.3 Interrupt Flag Status and Clear
- 16.8.4 Power and Clocks Status
- 16.8.5 External Multipurpose Crystal Oscillator (XOSC) Control
- 16.8.6 32kHz External Crystal Oscillator (XOSC32K) Control
- 16.8.7 32kHz Internal Oscillator (OSC32K) Control
- 16.8.8 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
- 16.8.9 8MHz Internal Oscillator (OSC8M) Control
- 16.8.10 DFLL48M Control
- 16.8.11 DFLL48M Value
- 16.8.12 DFLL48M Multiplier
- 16.8.13 DFLL48M Synchronization
- 16.8.14 3.3V Brown-Out Detector (BOD33) Control
- 16.8.15 Voltage Regulator System (VREG) Control
- 16.8.16 Voltage References System (VREF) Control
- 17. WDT – Watchdog Timer
- 18. RTC – Real-Time Counter
- 18.1 Overview
- 18.2 Features
- 18.3 Block Diagram
- 18.4 Signal Description
- 18.5 Product Dependencies
- 18.6 Functional Description
- 18.7 Register Summary
- 18.8 Register Description
- 18.8.1 Control
- 18.8.2 Read Request
- 18.8.3 Event Control
- 18.8.4 Interrupt Enable Clear
- 18.8.5 Interrupt Enable Set
- 18.8.6 Interrupt Flag Status and Clear
- 18.8.7 Status
- 18.8.8 Debug Control
- 18.8.9 Frequency Correction
- 18.8.10 Counter Value
- 18.8.11 Clock Value
- 18.8.12 Counter Period
- 18.8.13 Compare n Value
- 18.8.14 Alarm n Value
- 18.8.15 Alarm n Mask
- 19. EIC – External Interrupt Controller
- 20. NVMCTRL – Non-Volatile Memory Controller
- 20.1 Overview
- 20.2 Features
- 20.3 Block Diagram
- 20.4 Signal Description
- 20.5 Product Dependencies
- 20.6 Functional Description
- 20.7 Register Summary
- 20.8 Register Description
- 21. PORT
- 21.1 Overview
- 21.2 Features
- 21.3 Block Diagram
- 21.4 Signal Description
- 21.5 Product Dependencies
- 21.6 Functional Description
- 21.7 Register Summary
- 21.8 Register Description
- 21.8.1 Data Direction
- 21.8.2 Data Direction Clear
- 21.8.3 Data Direction Set
- 21.8.4 Data Direction Toggle
- 21.8.5 Data Output Value
- 21.8.6 Data Output Value Clear
- 21.8.7 Data Output Value Set
- 21.8.8 Data Output Value Toggle
- 21.8.9 Data Input Value
- 21.8.10 Control
- 21.8.11 Write Configuration
- 21.8.12 Peripheral Multiplexing n
- 21.8.13 Pin Configuration y
- 22. EVSYS – Event System
- 23. SERCOM – Serial Communication Interface
- 24. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
- 24.1 Overview
- 24.2 Features
- 24.3 Block Diagram
- 24.4 Signal Description
- 24.5 Product Dependencies
- 24.6 Functional Description
- 24.7 Register Summary
- 24.8 Register Description
- 25. SERCOM SPI – SERCOM Serial Peripheral Interface
- 25.1 Overview
- 25.2 Features
- 25.3 Block Diagram
- 25.4 Signal Description
- 25.5 Product Dependencies
- 25.6 Functional Description
- 25.7 Register Summary
- 25.8 Register Description
- 26. SERCOM I2C – SERCOM Inter-Integrated Circuit
- 26.1 Overview
- 26.2 Features
- 26.3 Block Diagram
- 26.4 Signal Description
- 26.5 Product Dependencies
- 26.6 Functional Description
- 26.7 Register Summary
- 26.8 Register Description
- 27. TC – Timer/Counter
- 27.1 Overview
- 27.2 Features
- 27.3 Block Diagram
- 27.4 Signal Description
- 27.5 Product Dependencies
- 27.6 Functional Description
- 27.7 Register Summary
- 27.8 Register Description
- 27.8.1 Control A
- 27.8.2 Read Request
- 27.8.3 Control B Clear
- 27.8.4 Control B Set
- 27.8.5 Control C
- 27.8.6 Debug Control
- 27.8.7 Event Control
- 27.8.8 Interrupt Enable Clear
- 27.8.9 Interrupt Enable Set
- 27.8.10 Interrupt Flag Status and Clear
- 27.8.11 Status
- 27.8.12 Counter Value
- 27.8.13 Period Value
- 27.8.14 Compare/Capture
- 28. ADC – Analog-to-Digital Converter
- 28.1 Overview
- 28.2 Features
- 28.3 Block Diagram
- 28.4 Signal Description
- 28.5 Product Dependencies
- 28.6 Functional Description
- 28.6.1 Principle of Operation
- 28.6.2 Basic Operation
- 28.6.3 Prescaler
- 28.6.4 ADC Resolution
- 28.6.5 Differential and Single-Ended Conversions
- 28.6.6 Accumulation
- 28.6.7 Averaging
- 28.6.8 Oversampling and Decimation
- 28.6.9 Window Monitor
- 28.6.10 Offset and Gain Correction
- 28.6.11 Interrupts
- 28.6.12 Events
- 28.6.13 Sleep Mode Operation
- 28.6.14 Synchronization
- 28.7 Register Summary
- 28.8 Register Description
- 28.8.1 Control A
- 28.8.2 Reference Control
- 28.8.3 Average Control
- 28.8.4 Sampling Time Control
- 28.8.5 Control B
- 28.8.6 Window Monitor Control
- 28.8.7 Software Trigger
- 28.8.8 Input Control
- 28.8.9 Event Control
- 28.8.10 Interrupt Enable Clear
- 28.8.11 Interrupt Enable Set
- 28.8.12 Interrupt Flag Status and Clear
- 28.8.13 Status
- 28.8.14 Result
- 28.8.15 Window Monitor Lower Threshold
- 28.8.16 Window Monitor Upper Threshold
- 28.8.17 Gain Correction
- 28.8.18 Offset Correction
- 28.8.19 Calibration
- 28.8.20 Debug Control
- 29. AC – Analog Comparators
- 29.1 Overview
- 29.2 Features
- 29.3 Block Diagram
- 29.4 Signal Description
- 29.5 Product Dependencies
- 29.6 Functional Description
- 29.7 Additional Features
- 29.8 Register Summary
- 29.9 Register Description
- 30. DAC – Digital-to-Analog Converter
- 30.1 Overview
- 30.2 Features
- 30.3 Block Diagram
- 30.4 Signal Description
- 30.5 Product Dependencies
- 30.6 Functional Description
- 30.7 Register Summary
- 30.8 Register Description
- 31. PTC - Peripheral Touch Controller
- 32. Electrical Characteristics
- 32.1 Disclaimer
- 32.2 Absolute Maximum Ratings
- 32.3 General Operating Ratings
- 32.4 Supply Characteristics
- 32.5 Maximum Clock Frequencies
- 32.6 Power Consumption
- 32.7 I/O Pin Characteristics
- 32.8 Analog Characteristics
- 32.8.1 Voltage Regulator Characteristics
- 32.8.2 Power-On Reset (POR) Characteristics
- 32.8.3 Brown-Out Detectors Characteristics
- 32.8.4 Analog-to-Digital (ADC) characteristics
- 32.8.5 Digital to Analog Converter (DAC) Characteristics
- 32.8.6 Analog Comparator Characteristics
- 32.8.7 Bandgap Reference Characteristics
- 32.8.8 Temperature Sensor Characteristics
- 32.9 NVM Characteristics
- 32.10 Oscillators Characteristics
- 32.10.1 Crystal Oscillator (XOSC) Characteristics
- 32.10.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
- 32.10.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
- 32.10.4 32.768kHz Internal oscillator (OSC32K) Characteristics
- 32.10.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
- 32.10.6 8MHz RC Oscillator (OSC8M) Characteristics
- 32.11 PTC Typical Characteristics
- 32.12 Timing Characteristics
- 33. Packaging Information
- 34. Schematic Checklist
- 35. Errata
- 36. Datasheet Revision History
- Appendix A. Conventions
- Appendix B. Acronyms and Abbreviations
- Table of Contents

378
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
z Bit 16 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z Bits 15:14 – AMODE: Address Mode
These bits set the slave addressing mode when the frame format (CTRLA.FORM) with address is used. They are
unused in master mode.
Table 25-8. Address Mode
z Bits 13:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 6 – PLOADEN: Slave Data Preload Enable
Setting this bit will enable preloading of the slave shift register when there is no transfer in progress. If the _SS line
is high when DATA is written, it will be transferred immediately to the shift register.
z Bits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 2:0 – CHSIZE[2:0]: Character Size
Table 25-9. Character Size
AMODE[1:0] Name Description
0x0 MASK ADDRMASK is used as a mask to the ADDR register
0x1 2_ADDRS The slave responds to the two unique addresses in ADDR and ADDRMASK
0x2 RANGE
The slave responds to the range of addresses between and including ADDR
and ADDRMASK. ADDR is the upper limit
0x3 Reserved
CHSIZE[2:0] Name Description
0x0 8BIT 8 bits
0x1 9BIT 9 bits
0x2-0x7 Reserved