Datasheet

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Table Of Contents

Description
Features
1. Configuration Summary
2. Ordering Information
- 2.1 SAM D20E
- 2.2 SAM D20G
- 2.3 SAM D20J
3. Block Diagram
4. Pinout
- 4.1 SAM D20J
- 4.2 SAM D20G
- 4.3 SAM D20E
5. I/O Multiplexing and Considerations
- 5.1 Multiplexed Signals
- 5.2 Other Functions
  - 5.2.1 Oscillator Pinout
  - 5.2.2 Serial Wire Debug Interface Pinout
6. Signal Descriptions List
7. Power Supply and Start-Up Considerations
- 7.1 Power Domain Overview
- 7.2 Power Supply Considerations
- 7.3 Power-Up
- 7.4 Power-On Reset and Brown-Out Detector
8. Product Mapping
9. Memories
- 9.1 Embedded Memories
- 9.2 Physical Memory Map
- 9.3 Non-Volatile Memory (NVM) User Row Mapping
- 9.4 NVM Software Calibration Area Mapping
- 9.5 Serial Number
10. Processor and Architecture
- 10.1 Cortex-M0+ Processor
- 10.2 Nested Vector Interrupt Controller
  - 10.2.1 Overview
  - 10.2.2 Interrupt Line Mapping
- 10.3 High-Speed Bus Matrix
  - 10.3.1 Features
  - 10.3.2 Configuration
- 10.4 AHB-APB Bridge
- 10.5 PAC – Peripheral Access Controller
  - 10.5.1 Overview
- 10.6 Register Description
11. Peripherals Configuration Overview
12. DSU – Device Service Unit
- 12.1 Overview
- 12.2 Features
- 12.3 Block Diagram
- 12.4 Signal Description
- 12.5 Product Dependencies
- 12.6 Debug Operation
- 12.7 Chip-Erase
- 12.8 Programming
- 12.9 Intellectual Property Protection
- 12.10 Device Identification
  - 12.10.1 CoreSight Identification
  - 12.10.2 DSU Chip Identification Method:
- 12.11 Functional Description
- 12.12 Register Summary
- 12.13 Register Description
13. Clock System
- 13.1 Clock Distribution
- 13.2 Synchronous and Asynchronous Clocks
- 13.3 Register Synchronization
- 13.4 Enabling a Peripheral
- 13.5 On-demand, Clock Requests
- 13.6 Power Consumption vs Speed
- 13.7 Clocks after Reset
14. GCLK – Generic Clock Controller
- 14.1 Overview
- 14.2 Features
- 14.3 Block Diagram
- 14.4 Signal Description
- 14.5 Product Dependencies
- 14.6 Functional Description
- 14.7 Register Summary
- 14.8 Register Description
15. PM – Power Manager
- 15.1 Overview
- 15.2 Features
- 15.3 Block Diagram
- 15.4 Signal Description
- 15.5 Product Dependencies
- 15.6 Functional Description
- 15.7 Register Summary
- 15.8 Register Description
16. SYSCTRL – System Controller
- 16.1 Overview
- 16.2 Features
- 16.3 Block Diagram
- 16.4 Signal Description
- 16.5 Product Dependencies
- 16.6 Functional Description
- 16.7 Register Summary
- 16.8 Register Description
17. WDT – Watchdog Timer
- 17.1 Overview
- 17.2 Features
- 17.3 Block Diagram
- 17.4 Signal Description
- 17.5 Product Dependencies
- 17.6 Functional Description
- 17.7 Register Summary
- 17.8 Register Description
18. RTC – Real-Time Counter
- 18.1 Overview
- 18.2 Features
- 18.3 Block Diagram
- 18.4 Signal Description
- 18.5 Product Dependencies
- 18.6 Functional Description
- 18.7 Register Summary
- 18.8 Register Description
19. EIC – External Interrupt Controller
- 19.1 Overview
- 19.2 Features
- 19.3 Block Diagram
- 19.4 Signal Description
- 19.5 Product Dependencies
- 19.6 Functional Description
- 19.7 Register Summary
- 19.8 Register Description
20. NVMCTRL – Non-Volatile Memory Controller
- 20.1 Overview
- 20.2 Features
- 20.3 Block Diagram
- 20.4 Signal Description
- 20.5 Product Dependencies
- 20.6 Functional Description
- 20.7 Register Summary
- 20.8 Register Description
21. PORT
- 21.1 Overview
- 21.2 Features
- 21.3 Block Diagram
- 21.4 Signal Description
- 21.5 Product Dependencies
- 21.6 Functional Description
- 21.7 Register Summary
- 21.8 Register Description
22. EVSYS – Event System
- 22.1 Overview
- 22.2 Features
- 22.3 Block Diagram
- 22.4 Signal Description
- 22.5 Product Dependencies
- 22.6 Functional Description
- 22.7 Register Summary
- 22.8 Register Description
23. SERCOM – Serial Communication Interface
- 23.1 Overview
- 23.2 Features
- 23.3 Block Diagram
- 23.4 Signal Description
- 23.5 Product Dependencies
- 23.6 Functional Description
24. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
- 24.1 Overview
- 24.2 Features
- 24.3 Block Diagram
- 24.4 Signal Description
- 24.5 Product Dependencies
- 24.6 Functional Description
- 24.7 Register Summary
- 24.8 Register Description
25. SERCOM SPI – SERCOM Serial Peripheral Interface
- 25.1 Overview
- 25.2 Features
- 25.3 Block Diagram
- 25.4 Signal Description
- 25.5 Product Dependencies
- 25.6 Functional Description
- 25.7 Register Summary
- 25.8 Register Description
26. SERCOM I2C – SERCOM Inter-Integrated Circuit
- 26.1 Overview
- 26.2 Features
- 26.3 Block Diagram
- 26.4 Signal Description
- 26.5 Product Dependencies
- 26.6 Functional Description
- 26.7 Register Summary
- 26.8 Register Description
  - 26.8.1 I2C Slave Register Description
  - 26.8.2 I2C Master Register Description
27. TC – Timer/Counter
- 27.1 Overview
- 27.2 Features
- 27.3 Block Diagram
- 27.4 Signal Description
- 27.5 Product Dependencies
- 27.6 Functional Description
- 27.7 Register Summary
- 27.8 Register Description
28. ADC – Analog-to-Digital Converter
- 28.1 Overview
- 28.2 Features
- 28.3 Block Diagram
- 28.4 Signal Description
- 28.5 Product Dependencies
- 28.6 Functional Description
- 28.7 Register Summary
- 28.8 Register Description
29. AC – Analog Comparators
- 29.1 Overview
- 29.2 Features
- 29.3 Block Diagram
- 29.4 Signal Description
- 29.5 Product Dependencies
- 29.6 Functional Description
- 29.7 Additional Features
- 29.8 Register Summary
- 29.9 Register Description
30. DAC – Digital-to-Analog Converter
- 30.1 Overview
- 30.2 Features
- 30.3 Block Diagram
- 30.4 Signal Description
- 30.5 Product Dependencies
- 30.6 Functional Description
- 30.7 Register Summary
- 30.8 Register Description
31. PTC - Peripheral Touch Controller
- 31.1 Overview
- 31.2 Features
- 31.3 Block Diagram
- 31.4 Signal Description
- 31.5 Product Dependencies
  - 31.5.1 I/O Lines
  - 31.5.2 Clocks
- 31.6 Functional Description
32. Electrical Characteristics
- 32.1 Disclaimer
- 32.2 Absolute Maximum Ratings
- 32.3 General Operating Ratings
- 32.4 Supply Characteristics
- 32.5 Maximum Clock Frequencies
- 32.6 Power Consumption
- 32.7 I/O Pin Characteristics
- 32.8 Analog Characteristics
- 32.9 NVM Characteristics
- 32.10 Oscillators Characteristics
- 32.11 PTC Typical Characteristics
- 32.12 Timing Characteristics
33. Packaging Information
- 33.1 Thermal Considerations
  - 33.1.1 Thermal Resistance Data
  - 33.1.2 Junction Temperature
- 33.2 Package Drawings
- 33.3 Soldering Profile
34. Schematic Checklist
- 34.1 Introduction
- 34.2 Power Supply
  - 34.2.1 Power Supply Connections
- 34.3 External Analog Reference Connections
- 34.4 External Reset Circuit
- 34.5 Unused or Unconnected Pins
- 34.6 Clocks and Crystal Oscillators
- 34.7 Programming and Debug Ports
35. Errata
- 35.1 Revision D
- 35.2 Revision C
- 35.3 Revision B
- 35.4 Revision A
36. Datasheet Revision History
- 36.1 Rev. K – 05/2014
- 36.2 Rev. J – 12/2013
- 36.3 Rev. I – 12/2013
- 36.4 Rev. H – 10/2013
- 36.5 Rev. G – 10/2013
- 36.6 Rev. F – 10/2013
- 36.7 Rev. E – 09/2013
- 36.8 Rev. D – 08/2013
- 36.9 Rev. C – 07/2013
- 36.10 Rev. B – 07/2013
- 36.11 Rev. A – 06/2013
Appendix A. Conventions
- A.1 Numerical Notation
- A.2 Memory Size and Type
- A.3 Frequency and Time
- A.4 Registers and Bits
Appendix B. Acronyms and Abbreviations
Table of Contents

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

z Bit 17:16 – DOPO: Data Out Pinout

This bit defines the available pad configurations for data out (DO) and the serial clock (SCK). In slave operation,

the slave select line (_SS) is controlled by DOPO, while in master operation the _SS line is controlled by the port

configuration.

In master operation, DO is MOSI.

In slave operation, DO is MISO.

These bits are not synchronized.

Table 25-6. Data Out Pinout

z Bits 15:9 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to

zero when this register is written. These bits will always return zero when read.

z Bit 8 – IBON: Immediate Buffer Overflow Notification

This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.

0: STATUS.BUFOVF is asserted when it occurs in the data stream.

1: STATUS.BUFOVF is asserted immediately upon buffer overflow.

This bit is not synchronized.

z Bit 7 – RUNSTDBY: Run In Standby

This bit defines the functionality in standby sleep mode.

These bits are not synchronized.

Table 25-7. Run In Standby Configuration

z Bits 6:5 – Reserved

These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to

zero when this register is written. These bits will always return zero when read.

z Bits 4:2 – MODE: Operating Mode

These bits must be written to 0x2 or 0x3 to select the SPI serial communication interface of the SERCOM.

0x2: SPI slave operation

0x3: SPI master operation

These bits are not synchronized.

z Bit 1 – ENABLE: Enable

0: The peripheral is disabled or being disabled.

DOPO DO SCK Slave _SS Master _SS

0x0 PAD[0] PAD[1] PAD[2] System configuration

0x1 PAD[2] PAD[3] PAD[1] System configuration

0x2 PAD[3] PAD[1] PAD[2] System configuration

0x3 PAD[0] PAD[3] PAD[1] System configuration

RUNSTDBY Slave Master

0x0

Disabled. All reception is dropped,

including the ongoing transaction.

Generic clock is disabled when ongoing transaction is

finished. All interrupts can wake up the device.

0x1 Wake on Receive Complete interrupt.

Generic clock is enabled while in sleep modes. All

interrupts can wake up the device.