Datasheet

367
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
25.6.2.6 Transferring Data
Master
When configured as a master (CTRLA.MODE is 0x3), the _SS line can be located at any general purpose I/O pin, and
must be configured as an output. When the SPI is ready for a data transaction, software must pull the _SS line low.
When writing a character to the Data register (DATA), the character will be transferred to the shift register when the shift
register is empty. Once the contents of TxDATA have been transferred to the shift register, the Data Register Empty flag
in the Interrupt Flag Status and Clear register (INTFLAG.DRE) is set, and a new character can be written to DATA.
As each character is shifted out from the master, another character is shifted in from the slave. If the receiver is enabled
(CTRLA.RXEN is one), the contents of the shift register will be transferred to the two-level receive buffer. The transfer
takes place in the same clock cycle as the last data bit is shifted in, and the Receive Complete Interrupt flag in the
Interrupt Flag Status and Clear register (INTFLAG.RXC) will be set. The received data can be retrieved by reading
DATA.
When the last character has been transmitted and there is no valid data in DATA, the Transmit Complete Interrupt flag in
the Interrupt Flag Status and Clear register (INTFLAG.TXC) is set. When the transaction is finished, the master must
indicate this to the slave by pulling the _SS line high.
Slave
When configured as a slave (CTRLA.MODE is 0x2), the SPI interface will remain inactive, with the MISO line tri-stated as
long as the _SS pin is pulled high. Software may update the contents of DATA at any time, as long as the Data Register
Empty flag in the Interrupt Status and Clear register (INTFLAG.DRE) is set.
When _SS is pulled low and SCK is running, the slave will sample and shift out data according to the transaction mode
set. When the contents of TxDATA have been loaded into the shift register, INTFLAG.DRE is set, and new data can be
written to DATA. Similar to the master, the slave will receive one character for each character transmitted. On the same
clock cycle as the last data bit of a character is received, the character will be transferred into the two-level receive buffer.
The received character can be retrieved from DATA when INTFLAG.RCX is set.
When the master pulls the _SS line high, the transaction is done and the Transmit Complete Interrupt flag in the Interrupt
Flag Status and Clear register (TXC) is set.
Once DATA is written, it takes up to three SCK clock cycles before the content of DATA is ready to be loaded into the
shift register. When the content of DATA is ready to be loaded, this will happen on the next character boundary. As a
consequence, the first character transferred in a SPI transaction will not be the content of DATA. This can be avoided by
using the preloading feature.
Refer to “Preloading of the Slave Shift Register” on page 368.
When transmitting several characters in one SPI transaction, the data has to be written to DATA while there are at least
three SCK clock cycles left in the current character transmission. If this criteria is not met, then the previous character
received will be transmitted.
After the DATA register is empty, it takes three CLK_SERCOM_APB cycles for INTFLAG.DRE to be set.
25.6.2.7 Receiver Error Bit
The SPI receiver has one error bit: the Buffer Overflow bit (BUFOVF), which can be read from the Status register
(STATUS). Upon error detection, the bit will be set until it is cleared by writing a one to it. The bit is also automatically
cleared when the receiver is disabled.
There are two methods for buffer overflow notification. When the immediate buffer overflow notification bit (CTRLA.IBON)
is set, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by
reading RxDATA until the receive complete interrupt flag (INTFLAG.RXC) goes low.
When CTRLA.IBON is zero, the buffer overflow condition travels with data through the receive FIFO. After the received
data is read, STATUS.BUFOVF will be set along with INTFLAG.RXC, and RxDATA will be zero.