Datasheet

353
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
1: The transmitter is enabled or will be enabled when the USART is enabled.
Writing a zero to this bit will disable the USART transmitter. Disabling the transmitter will not become effective until
ongoing and pending transmissions are completed.
Writing a one to CTRLB.TXEN when the USART is disabled will set CTRLB.TXEN immediately. When the USART
is enabled, CTRLB.TXEN will be cleared, and STATUS.SYNCBUSY will be set and remain set until the transmitter
is enabled. When the transmitter is enabled, CTRLB.TXEN will read back as one.
Writing a one to CTRLB.TXEN when the USART is enabled will set STATUS.SYNCBUSY, which will remain set
until the receiver is enabled, and CTRLB.TXEN will read back as one.
This bit is not enable-protected.
z Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 13 – PMODE: Parity Mode
This bit selects the type of parity used when parity is enabled (CTRLA.FORM is one). The transmitter will automat-
ically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a
parity value for the incoming data and parity bit, compare it to the parity mode and, if a mismatch is detected, STA-
TUS.PERR will be set.
0: Even parity.
1: Odd parity.
This bit is not synchronized.
z Bit 12:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 9 – SFDE: Start of Frame Detection Enable
This bit controls whether the start-of-frame detector will wake up the device when a start bit is detected on the RxD
line, according to the table below.
This bit is not synchronized.
z Bits 8:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bit 6 – SBMODE: Stop Bit Mode
This bit selects the number of stop bits transmitted.
0: One stop bit.
1: Two stop bits.
This bit is not synchronized.
z Bits 5:3 – Reserved
SFDE INTENSET.RXS INTENSET.RXC Description
0 X X Start-of-frame detection disabled.
1 0 0 Reserved
1 0 1 Start-of-frame detection enabled. RXCIF wakes up the device from all sleep modes.
1 1 0 Start-of-frame detection enabled. RXSIF wakes up the device from all sleep modes.
1 1 1
Start-of-frame detection enabled. Both RXCIF and RXSIF wake up the device from
all sleep modes.