Datasheet

345
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
24.6.3.3 Start-of-Frame Detection
The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the internal
8MHz oscillator must be selected as the GCLK_SERCOMx_CORE source.
When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is
enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in relation
to the 8MHz Internal Oscillator start-up time. Refer to “Electrical Characteristics” on page 563 for details. The start-up
time of the 8MHz Internal Oscillator varies with supply voltage and temperature.
The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing a one
to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable
bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately
when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force
the 8MHz Internal Oscillator and USART clock active while the frame is being received, but the CPU will not wakeup until
the Receive Complete interrupt is generated, if enabled.
24.6.4 Interrupts
The USART has the following interrupt sources:
z Receive Start
z Receive Complete
z Transmit Complete
z Data Register Empty
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the USART is reset. See the register description for details on how to clear interrupt
flags.
The USART has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to
determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 25 for details.
24.6.5 Events
Not applicable.
24.6.6 Sleep Mode Operation
When using internal clocking, writing the Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) to one will
allow GCLK_SERCOMx_CORE to be enabled in all sleep modes. Any interrupt can wake up the device.
When using external clocking, writing a one to CTRLA.RUNSTDBY will allow the Receive Complete interrupt.to wake up
the device.
If CTRLA.RUNSTDBY is zero, the internal clock will be disabled when any ongoing transfer is finished. A Transfer
Complete interrupt can wake up the device. When using external clocking, this will be disconnected when any ongoing
transfer is finished, and all reception will be dropped.
24.6.7 Synchronization
Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be
synchronized when accessed. A register can require:
z Synchronization when written