Datasheet

343
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
24.6.2.5 Data Transmission
A data transmission is initiated by loading the DATA register with the data to be sent. The data in TxDATA is moved to
the shift register when the shift register is empty and ready to send a new frame. When the shift register is loaded with
data, one complete frame will be transmitted.
The Transmit Complete interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.TXC) is set, and the
optional interrupt is generated, when the entire frame plus stop bit(s) have been shifted out and there is no new data
written to the DATA register.
The DATA register should only be written when the Data Register Empty flag in the Interrupt Flag Status and Clear
register (INTFLAG.DRE) is set, which indicates that the register is empty and ready for new data.
Disabling the Transmitter
Disabling the transmitter will not become effective until any ongoing and pending transmissions are completed, i.e., when
the transmit shift register and TxDATA do not contain data to be transmitted. The transmitter is disabled by writing a zero
to the Transmitter Enable bit in the Control B register (CTRLB.TXEN).
24.6.2.6 Data Reception
The receiver starts data reception when a valid start bit is detected. Each bit that follows the start bit will be sampled at
the baud rate or XCK clock, and shifted into the receive shift register until the first stop bit of a frame is received. When
the first stop bit is received and a complete serial frame is present in the receive shift register, the contents of the shift
register will be moved into the two-level receive buffer. The Receive Complete interrupt flag in the Interrupt Flag Status
and Clear register (INTFLAG.RXC) is set, and the optional interrupt is generated. A second stop bit will be ignored by the
receiver.
The received data can be read by reading the DATA register. DATA should not be read unless the Receive Complete
interrupt flag is set.
Disabling the Receiver
Disabling the receiver by writing a zero to the Receiver Enable bit in the Control B register (CTRLB.RXEN) will flush the
two-level receive buffer, and data from ongoing receptions will be lost.
Error Bits
The USART receiver has three error bits. The Frame Error (FERR), Buffer Overflow (BUFOVF) and Parity Error (PERR)
bits can be read from the Status (STATUS) register. Upon error detection, the corresponding bit will be set until it is
cleared by writing a one to it. These bits are also automatically cleared when the receiver is disabled.
There are two methods for buffer overflow notification. When the immediate buffer overflow notification bit (CTRLA.IBON)
is set, STATUS.BUFOVF is raised immediately upon buffer overflow. Software can then empty the receive FIFO by
reading RxDATA until the receive complete interrupt flag (INTFLAG.RXC) goes low.
When CTRLA.IBON is zero, the buffer overflow condition travels with data through the receive FIFO. After the received
data is read, STATUS.BUFOVF will be set along with INTFLAG.RXC.
Asynchronous Data Reception
The USART includes a clock recovery and data recovery unit for handling asynchronous data reception. The clock
recovery logic is used to synchronize the incoming asynchronous serial frames at the RxD pin to the internally generated
baud-rate clock. The data recovery logic samples and applies a low-pass filter to each incoming bit, thereby improving
the noise immunity of the receiver. The asynchronous reception operational range depends on the accuracy of the
internal baud-rate clock, the rate of the incoming frames and the frame size (in number of bits).
Asynchronous Operational Range
The operational range of the receiver depends on the difference between the received bit rate and the internally
generated baud rate. If the baud rate of an external transmitter is too high or too low compared to the internally generated
baud rate, the receiver will not be able to synchronize the frames to the start bit.
There are two possible sources for a mismatch in baud rate. The reference clock will always have some minor instability.
In addition, the baud-rate generator can not always do an exact division of the reference clock frequency to get the baud