Datasheet

342
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Figure 24-3. Clock Generation
Synchronous Clock Operation
When synchronous mode is used, the CTRLA.MODE bit group controls whether the transmission clock (XCK line) is an
input or output. The dependency between the clock edges and data sampling or data change is the same for internal and
external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge as data is driven on the TxD pin.
The Clock Polarity bit in the Control A register (CTRLA.CPOL) selects which XCK clock edge is used for RxD sampling
and which is used for TxD change. As shown in Figure 24-4, when CTRLA.CPOL is zero, the data will be changed on the
rising XCK edge and sampled on the falling XCK edge. If CTRLA.CPOL is one, the data will be changed on the falling
edge of XCK and sampled on the rising edge of XCK.
Figure 24-4. Synchronous Mode XCK Timing
When the clock is provided through XCK (CTRLA.MODE is 0x0), the shift registers operate directly on the XCK clock.
This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the
system frequency.
24.6.2.4 Data Register
The USART Transmit Data register (TxDATA) and USART Receive Data register(RxDATA) share the same I/O address,
referred to as the Data register (DATA). Writing the DATA register will update the Transmit Data register. Reading the
DATA register will return the contents of the Receive Data register.
XCK
Baud Rate Generator
Base
Period
/2
/2 /16/1
CTRLA.CMODE
0
1
1
0
Tx Clk
Rx Clk
1
0
Internal Clk
(GCLK)
CTRLA.MODE[0]
/8
0
1
Sample
RxD / TxD
XCK
CTRLA.CPOL=1
Sample
RxD / TxD
XCK
CTRLA.CPOL=0
Change
Change