Datasheet

327
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
22.8.7 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18
Reset: 0x00000000
Property: –
z Bits 31:16 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z Bits 15:8 – EVDx: Event Detected Channel x
This flag is set on the next CLK_EVSYS_APB cycle when an event is being propagated through the channel, and
an interrupt request will be generated if INTENCLR/SET.EVDx is one.
When the event channel path is asynchronous, the EVDx interrupt flag will not be set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Event Detected Channel n interrupt flag.
z Bits 7:0 – OVRx: Overrun Channel x
This flag is set on the next CLK_EVSYS cycle after an overrun channel condition occurs, and an interrupt request
will be generated if INTENCLR/SET.OVRx is one.
There are two possible overrun channel conditions:
z One or more of the event users on channel x are not ready when a new event occurs
z An event happens when the previous event on channel x has not yet been handled by all event users
When the event channel path is asynchronous, the OVRx interrupt flag will not be set.
Bit3130292827262524
AccessRRRRRRRR
Reset00000000
Bit2322212019181716
AccessRRRRRRRR
Reset00000000
Bit151413121110 9 8
EVD7 EVD6 EVD5 EVD4 EVD3 EVD2 EVD1 EVD0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000
Bit76543210
OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset00000000